I.MX6 Sabrelite With PCIe(Change TLP Size)

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I.MX6 Sabrelite With PCIe(Change TLP Size)

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zhaopingyang_sg
Contributor III

I want to know how to change Data size in one read tlp and Data size in one write tlp? Current  value is 8 for write, and 16 for Read.

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zhaopingyang_sg
Contributor III

I have read the example i.MX6Q PCIe EP/RC Validation System ​ and What is the PCIe i.MX6 max payload size 。but I do not find Code about how to change the TLP size. do you have the test code.??

thank you..

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igorpadykov
NXP Employee
NXP Employee

what do you mean by "TLP size",  payload ?

Max payload size determined by EP capability and its submitted in

Config space by EP when its enumerated by RC.

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zhaopingyang_sg
Contributor III

I want to use PCIE  transfer data to FPGA,But the I.MX6 SDMA do not Support PCIE. So  I use memcpy function to get data From FPGA.  FPGA engineer tell me each read request just read 16 Bytes from FPGA,and each write just write 8 bytes.How can I Improve performance ?

follow is PCIe Host config space content:

vendor ID =                   0x16c3

device ID =                   0xabcd

command register =            0x0007

status register =             0x0010

revision ID =                 0x01

class code =                  0x06

sub class code =              0x04

programming interface =       0x00

cache line =                  0x08

latency time =                0x00

header type =                 0x01

BIST =                        0x00

base address 0 =              0x01200000

base address 1 =              0x00000000

primary bus number =          0x00

secondary bus number =        0x01

subordinate bus number =      0x01

secondary latency timer =     0x00

IO base =                     0xf1

IO limit =                    0x01

secondary status =            0x0000

memory base =                 0x0100

memory limit =                0x0110

prefetch memory base =        0xfff1

prefetch memory limit =       0x0001

prefetch memory base upper =  0x00000000

prefetch memory limit upper = 0x00000000

IO base upper 16 bits =       0xffff

IO limit upper 16 bits =      0x000f

expansion ROM base address =  0x00000000

interrupt line =              0x9b

interrupt pin =               0x01

bridge control =              0x0000

Capabilities - Power Management

Capabilities - Message Signaled Interrupts: 0x50 control 0x180 Disabled, 64-bit, MME: 0 MMC: 0

        Address: 0000000000000000  Data: 0x0000

        Per-vector Mask: Support Mask Bit: 0x0, Pending Bit: 0x0

Capabilities - PCIe: Root Port, IRQ 0

        Device: Max Payload: 128 bytes, Extended Tag: 5-bit

                Acceptable Latency: L0 - <64ns, L1 - <1us

                Errors Enabled: Relaxed Ordering

        Max Read Request 512 bytes

        Link: MAX Speed - 5.0Gb/s, MAX Width - by 1 Port - 0 ASPM - L0s & L1

                Latency: L0s - <1us, L1 - <8us

                ASPM - Disabled, RCB - 64bytes

                Speed - 2.5Gb/s, Width - by 1

        Root Control Enabled:

Ext Capabilities - Advanced Error Reporting. 0x100. Version 1. AER Control: 0xa0

   Uncorrectable : Mask 0x0. Severity 0x62030

   Uncorrectable Status:    Correctable : Mask 0x2000.

   Correctable Status:

   HeaderLog:

   Error Source Identification: 0x0 0x0

Ext Capabilities - Virtual Channel. 0x140. Version 1

thanks!!

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igorpadykov
NXP Employee
NXP Employee

in suggested link there is example with ipu dma.

There is no SW mechanism to specify the exact number of the bytes in one TLP,

and as answered on https://community.nxp.com/docs/DOC-95014

MAX_PAY_LOAD_SIZE of imx6 pcie is 128bytes.

The actual data size on one tlp is decided by the cache-burst capability of the pcie master.

That's why the data size in the imx6 pcie ep/rc validation is 32 when arm core is used

as the bus master. And the data size is 64 when IPU(DMA) used as the bus master.

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1,006 Views
zhaopingyang_sg
Contributor III

Follow the i.MX6Q PCIe EP/RC Validation System ,the test function use TLP Payload size is 8 and 32 Bytes for Write , 32 and 64 for read。if no SW mechanism to specify the exact number of the bytes in one TLP,how did it finish the test?could you give me the test source code?

And cache-burst capability Can not be changed by SW?

thinks!

1,006 Views
igorpadykov
NXP Employee
NXP Employee

Hi zhaoping

please look at examples in

i.MX6Q PCIe EP/RC Validation System

What is the PCIe i.MX6 max payload size ?

Best regards

igor

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