HSADC MUX ISSUE

[lpcware]

Content originally posted in LPCWare by jinnuudn on Thu Dec 04 02:42:44 MST 2014
Hi

I'm currently using HSADC of LPC4370 .I'm feeding analog input to channel 1 i.e(ADC1) but in HSADC configuration i'm configuring channel 0 i.e,(ADC0).according to this i suppose to get junk data but i'm getting Channel 1(ADC1) data at the adc ouput .Please find the below HASDC configuration code



/**
* @briefmain routine for HSADC example
* @returnFunction should not exit
*/

uint32_t freqHSADC = 0;
uint8_t FIFO_TRIP_POINT = 8;
void hsadc_Cfg(int HSADCChannel_Num)
{
/* Setting up the HSADC clock is more complex than other peripherals.
   The HSADC clock is driven directly from the CGU/CCU and has limited
   source and divider options. Because the HSADC clocking is entirely
   handled outside the HSADC peripheral, example code for setting up
   the CGU/CCU to get a rough HSADC clock rate is included in this
   example. */
//setupClock(HSADC_CLOCK_RATE);

/* SetUp HSADC Clock */
hsadc_ClockSetUp();

/* Initialize HSADC */
Chip_HSADC_Init(LPC_ADCHS);

/* Setup FIFO trip points for interrupt/DMA set to FIFO_TRIP_POINT sample, enabling packing */
Chip_HSADC_SetupFIFO(LPC_ADCHS, FIFO_TRIP_POINT, true);


/* Show the actual HSADC clock rate */
freqHSADC = Chip_HSADC_GetBaseClockRate(LPC_ADCHS);
DEBUGOUT("HSADC sampling rate = %dKHz\r\n", freqHSADC / 1000);

/* Enable HSADC interrupts in NVIC */
NVIC_ClearPendingIRQ(ADCHS_IRQn);
NVIC_DisableIRQ(ADCHS_IRQn);

Chip_HSADC_ClearIntStatus(LPC_ADCHS, 0, ( HSADC_INT0_FIFO_FULL | HSADC_INT0_FIFO_EMPTY |
                                  HSADC_INT0_FIFO_OVERFLOW | HSADC_INT0_DSCR_DONE |
                                  HSADC_INT0_DSCR_ERROR | HSADC_INT0_ADC_OVF |
                                  HSADC_INT0_ADC_UNF));

Chip_HSADC_ClearIntStatus(LPC_ADCHS, 1, ( HSADC_INT1_THCMP_BRANGE(HSADCChannel_Num) | HSADC_INT1_THCMP_ARANGE(HSADCChannel_Num) |
                                  HSADC_INT1_THCMP_DCROSS(HSADCChannel_Num) | HSADC_INT1_THCMP_UCROSS(HSADCChannel_Num)  |
                                  HSADC_INT1_OVERRUN(HSADCChannel_Num) ));


/* Show the actual HSADC clock rate */
freqHSADC = Chip_HSADC_GetBaseClockRate(LPC_ADCHS);
DEBUGOUT("HSADC sampling rate = %dKHz\r\n", freqHSADC / 1000);

// Make sure the HADC is not powered down
LPC_ADCHS->POWER_DOWN = (0<<0);        /* PD_CTRL:      0=disable power down, 1=enable power down */

/* Flush HADC FIFO*/
Chip_HSADC_FlushFIFO(LPC_ADCHS);

/* Setup FIFO trip points for interrupt/DMA set to FIFO_TRIP_POINT sample, enabling packing */
//Chip_HSADC_SetupFIFO(LPC_ADCHS, FIFO_TRIP_POINT, true);
//Chip_HSADC_SetupFIFO(LPC_ADCHS, FIFO_TRIP_POINT, false);

/* Software trigger only, 0x90 recovery clocks, add channel IF to FIFO entry */
Chip_HSADC_ConfigureTrigger(LPC_ADCHS, HSADC_CONFIG_TRIGGER_SW,
HSADC_CONFIG_TRIGGER_RISEEXT, HSADC_CONFIG_TRIGGER_NOEXTSYNC,
HSADC_CHANNEL_ID_EN_ADD, 0x90);

/* Select both positive and negative DC biasing for input 0 */
Chip_HSADC_SetACDCBias(LPC_ADCHS, HSADCChannel_Num, HSADC_CHANNEL_DCBIAS, HSADC_CHANNEL_NODCBIAS);

/* Setup data format for offset binary and update clock settings. This function
   should be called whenever a clock change is made to the HSADC */
Chip_HSADC_SetPowerSpeed(LPC_ADCHS, false);

/* Enable HSADC power */ /* little bit doubt full, i think it is  not turning on power */
//Chip_HSADC_EnablePower(LPC_ADCHS);
LPC_ADCHS->POWER_CONTROL |= ((1 << 17) |     /* POWER_SWITCH: 0=ADC is power gated, 1=ADC is active */
                         (1 << 18));      /* BGAP_SWITCH:  0=ADC bandgap reg is power gated, 1=ADC bandgap is active */

/* Setup HSADC table 0 descriptors */
/* Descriptor entries are mapped as follows */
/* 0 : mapped to input 0, branch to next descriptor table after sample, match time
   is 0x90 clocks for the initial sample (must be greater than or equal to
     recovery clocks for auto power-up), */
Chip_HSADC_SetupDescEntry(LPC_ADCHS, 0, 0, (HSADC_DESC_CH(HSADCChannel_Num) |
                                    HSADC_DESC_BRANCH_SWAP | HSADC_DESC_MATCH(0x90) | HSADC_DESC_THRESH_NONE |
HSADC_DESC_RESET_TIMER));
/* Setup HSADC table 1 des ccriptors */
/* 0 : mapped to input 0, branch to next descriptor after sample, match time
   is 1 */
Chip_HSADC_SetupDescEntry(LPC_ADCHS, 1, 0, (HSADC_DESC_CH(HSADCChannel_Num) |
                                    HSADC_DESC_BRANCH_FIRST | HSADC_DESC_MATCH(1) | HSADC_DESC_THRESH_NONE |
HSADC_DESC_RESET_TIMER));

/* Setup HSADC interrupts on group 0 - FIFO trip (full), FIFO overrun
   error, and descriptor statuses */

//Chip_HSADC_EnableInts(LPC_ADCHS, 0, ( HSADC_INT0_FIFO_OVERFLOW | HSADC_INT0_FIFO_FULL | HSADC_INT0_DSCR_ERROR));

Chip_HSADC_EnableInts(LPC_ADCHS, 0, HSADC_INT0_FIFO_OVERFLOW);

/* Enable HSADC interrupts in NVIC */
NVIC_ClearPendingIRQ(ADCHS_IRQn);
NVIC_EnableIRQ(ADCHS_IRQn);

/* Update descriptor tables - needed after updating any descriptors */
Chip_HSADC_UpdateDescTable(LPC_ADCHS, 0);

/* Update descriptor tables - needed after updating any descriptors */
Chip_HSADC_UpdateDescTable(LPC_ADCHS, 1);

}



void ADCHS_IRQHandler(void)
{
uint32_t sts, data, sample, ch;
static bool on;

/* Toggle LED on each sample interrupt */
on = !on;
//Board_LED_Set(0, on);

/* Get threshold interrupt status on group 1 and toggle on any crossing */
sts = Chip_HSADC_GetIntStatus(LPC_ADCHS, 1) & Chip_HSADC_GetEnabledInts(LPC_ADCHS, 1);
if (sts & (HSADC_INT1_THCMP_DCROSS(0) | HSADC_INT1_THCMP_DCROSS(0) |
   HSADC_INT1_THCMP_UCROSS(0) | HSADC_INT1_THCMP_UCROSS(0) |
   HSADC_INT1_THCMP_DCROSS(0) | HSADC_INT1_THCMP_UCROSS(0))) {
//Board_LED_Set(1, true);
}
else {
//Board_LED_Set(1, false);
}

/* Clear threshold interrupts statuses */
Chip_HSADC_ClearIntStatus(LPC_ADCHS, 1, sts);

/* Get ADC interrupt status on group 0 */
sts = Chip_HSADC_GetIntStatus(LPC_ADCHS, 0) & Chip_HSADC_GetEnabledInts(LPC_ADCHS, 0);

/* Set LED 2 (if it exists) on an error */
if (sts & (HSADC_INT0_FIFO_OVERFLOW | HSADC_INT0_DSCR_ERROR)) {
//Board_LED_Set(2, true);
}
else {
//Board_LED_Set(2, false);
}

/* Clear group 0 interrupt statuses */
Chip_HSADC_ClearIntStatus(LPC_ADCHS, 0, sts);
}

void hsadc_ClockSetUp(void){
Chip_USB0_Init(); /* Initialize the USB0 PLL to 480 MHz */
Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_USBPLL, 2); /* Source DIV_A from USB0PLL, and set divider to 2 (Max div value supported is 4)  [IN 480 MHz; OUT 240 MHz */
Chip_Clock_SetDivider(CLK_IDIV_B, CLKIN_IDIVA, 3); /* Source DIV_B from DIV_A, [IN 240 MHz; OUT 40 MHz */
Chip_Clock_SetBaseClock(CLK_BASE_ADCHS, CLKIN_IDIVB, true, false); /* Source ADHCS base clock from DIV_B */
Chip_Clock_EnableOpts(CLK_ADCHS, true, true, 1); /* Enable the clock */
}

kindly let me know where i'm wrong or is am missing any configuration related to muxing.

Thanks in advance .

Regards,
Jineshwar