Affect of SVR modification on P2041

[ayhmi]

Hello,

We are using a P2041 architecture board. On FAQ section (P2040/P2041Hardware Specifications/Reference Manual Specific FAQs ) there is a bullet about SVR modification:

P2041 Hardware spec mentions that local bus address pins LA16 and LA17 must not be pulled down during power-on reset, while P204x RDB Schematics document mentions that LA17 and LA16 are pulled down optionally for CFG_SVR [1:0]. Can you please clarify?

Pin LA17 and LA16 are POR pins for CFG_SVR [1:0], and they have internal weak pull-up. To get correct SVR value for P2041, pin LA17 needs external pull low.

LA16 = 1 and LA17 = 1 for P2040. LA16 = 1 and LA17 = 0 for P2041.

On our hardware side LA16 and LA17 are left open so the SVR register is observed as P2040. I've modified the u-boot firmware not to check for SVR for L2 cache enabling. So now it enables L2. Does the L2 cache is now usable or not?

Also there are some differences related with core clock speed. on P2040 it says clock can be up to 1200 MHz but we are running our cores on 1300 MHz. Are we overclocking the processor or system is working fine?

My question is: Does the SVR modification on P2041 affects the working condition of the processor or just affects the SVR register?

Thanks In advance,

Omer

[ayhmi]

Thanks for the reply ufedor.

Our part number is P2041NXN7NNC.

So you say we actually can't use L2 cache right?

Is it ok that we use our cores on 1300 MHz? Since our P2041 seems to be supporting 1333 MHz.

[ufedor]

> So you say we actually can't use L2 cache right?

Vice-versa.

The L2 Cache initialization and usage is identical for P2040 and P2041.

> Is it ok that we use our cores on 1300 MHz? Since our P2041 seems to be supporting 1333 MHz.

Yes, it is possible to run cores at 1300 MHz in the described case (i.e. for the part P2041NXN7NNC).

[ufedor]

When LA16 = 1 and LA17 = 0 the SOC during POR is configured as P2041 and has the following differences from the P2040:

- P2041 also supports 128-Kbyte private backside cache for each of the cores;

- P2041 also supports a 10 Gbps Ethernet (XAUI) Controller.

You wrote:

> P204x RDB Schematics document mentions that

> LA17 and LA16 are pulled down optionally for CFG_SVR [1:0].

Please refer to the AN4402 - P2041/P2040 QorIQ Integrated Processor Design Checklist, Table 6. Reset configuration pins.

> On our hardware side LA16 and LA17 are left open so

> the SVR register is observed as P2040. I've modified

> the u-boot firmware not to check for SVR for L2 cache enabling.

This description is not clear because both processors (P2040 and P2041) have identical 1024-Kbyte Frontside CoreNet Platform Cache.

> on P2040 it says clock can be up to 1200 MHz but

> we are running our cores on 1300 MHz.

What is the exact part number on the processor's case top?