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Affect of SVR modification on P2041

Question asked by Omer Eskizara on May 24, 2016
Latest reply on May 24, 2016 by ufedor



We are using a P2041 architecture board. On FAQ section (P2040/P2041Hardware Specifications/Reference Manual Specific FAQs ) there is a bullet about SVR modification:

P2041 Hardware spec mentions that local bus address pins LA16 and LA17 must not be pulled down during power-on reset, while P204x RDB Schematics document mentions that LA17 and LA16 are pulled down optionally for CFG_SVR [1:0]. Can you please clarify?

Pin LA17 and LA16 are POR pins for CFG_SVR [1:0], and they have internal weak pull-up. To get correct SVR value for P2041, pin LA17 needs external pull low.

LA16 = 1 and LA17 = 1 for P2040. LA16 = 1 and LA17 = 0 for P2041.


On our hardware side LA16 and LA17 are left open so the SVR register is observed as P2040. I've modified the u-boot firmware not to check for SVR for L2 cache enabling. So now it enables L2. Does the L2 cache is now usable or not?


Also there are some differences related with core clock speed. on P2040 it says clock can be up to 1200 MHz but we are running our cores on 1300 MHz. Are we overclocking the processor or system is working fine?


My question is: Does the SVR modification on P2041 affects the working condition of the processor or just affects the SVR register?


Thanks In advance,