I.MX6 LPDDR2 2x32 mode calibrations

[AndyHo]

Hi ,

We have a IMX6 custom board, LPDDR2 in 2x32 mode, MMDC0 CS0/1, MMDC1 CS0/1 are used.

There is a  sample implementation is based on the document released by NXP,

http://www.nxp.com/files/32bit/doc/app_note/AN4467.pdf, in sec 19, and it has been merged into mainline uboot, why not the calibration can be done in realtime?

Actually some of our boards random fail during android burning test, we need to recalibration again and again to find another suitable calibrated parameters for those boards, I doubt the ddr stress tool (1.03 lpddr2) calibration result is not  for all chip selects.

In this application note, some calibrations are implemented for x32 (MMDC0) or DDR3 X64 only, so I do the samething for MMDC1 (2x32, I think), it should be work for MMDC1, but the test result is fail, so I double check the registers in refernce manual (2014/06 rev02), and found some questions in refernce manual and application note.

Question 1: ZQ calibration

In the imx6 ddr calibration application note page 13, you can see the description in list:

For DDR3:

MMDC0_MPZQHWCTRL          

For LPDDR2 2-Channel

MMDC0_MPZQHWCTRL

MMDC1_MPZQHWCTRL

-----------------------------------------------------------------

ZQ_PARA_EN

-----------------------------------------------------------------

Device ZQ calibration parallel enable.

0- Device ZQ calibration is done in serial (CSD0 first and then CSD1).

1- ZQ calibration of both CS is done in parallel, In functional mode, parallel calibration should be preferred for its speed. Choose serial as a for debugging, if ZQ calibration issues are suspected

but I can't found ZQ_PARA_EN field in reference manual, where is it? and it cause question 4.

Quesiton 2:ZQ calibration

In the imx6 ddr calibration application note sample code, the MMDC0 and MMDC1 perform dqs/read/write calibration separately, does it means every calibration should perform 4 times in LPDDR2 2x32 mode?( MMDC0 and MMDC1,each CS0 and CS1)? the question is related to the question 3,4

Question 3: all calibration,

Before assert ZQ calibration, you must assign CALIB_PER_CS (CS0 or CS1) in MMDCx_MDMISC, In our design 4 cs are used, does it means only one cs of MMDC can be calibrated and another is ignore? which cs is targetted for ZQ calibration in ddr stress tester? we found system get more stable if we disable cs1 access of MMDC0 & 1(ex: 2GB->1GB). so I doubt ddr stress tester only calibration one of cs of each channel

Question 4:

ZQ calibration, In Reference manual 44.12.31 MMDC PHY ZQ HW control register(MMDCx_MPZQHWCTRL), you can see the description:

Supported Mode Of Operations:
For Channel 0: All
For Channel 1: This register is reserved for channel 1. Channel 1 ZQ is also controlled by MMDC0_MPZQHWCTRL.

you can force a MMDC0 ZQ calibration by assert ZQ_HW_FOR, but how to do it for MMDC1 since it's control by MMDC0? What does the Reserved means? In my test result, MMDC1 ZQ_HW_PD_RES/ZQ_HW_PU_RES are 0x00000000, it means MMDC1 is not perform ZQ calibration even I set one of/both MMDCx_MPZQHWCTRL to 0xA1390003.

Question 5:Write leveling calibration

In ddr calibration application note:

3.2 LPDDR2

All the above calibration processes except DQS gating calibration and write leveling calibration can be

used for LPDDR2 calibration.

In reference manual page 3883, you can see the description:

NOTE
In LPDDR2 mode Write-leveling calibration should be disabled.

But in 44.12.33 MMDC PHY Write Leveling Configuration and Error Status Register (MMDCx_MPWLGCR)

Supported Mode Of Operations:
For Channel 0: All
For Channel 1: DDR3_x64, LP2_2ch_x16, LP2_2ch_x32

Is the write leveling calibration necessary for LPDDR2?.

Question 6, Read DQS calibration:
Same as Question 2, only cs0 or cs1 is targetted of each MMDC for read dqs calibraiton? which cs is targetted for ZQ calibration in ddr stress tester? should we target the cs1 for the calibraiton? I am afraid only cs0 or cs1 is calibrated in my case.

Question 7, Read DQS calibration:

In ddr calibration application note:

3.2 LPDDR2

All the above calibration processes except DQS gating calibration and write leveling calibration can be

used for LPDDR2 calibration.

I found the read/write delay calibration always fail if I bypass read DQS calibration, but the read DQS calibration register is only for DDR3( see below register description)? is it neccesary to perform read DQS calibration before read/write delay calibration? please note that read/write delay calibration is imx only, not standard, I don't know why I can't bypass read DQS calibration like ddr stress tester did.

44.12.46 MMDC PHY Read DQS Gating Control Register 0(MMDCx_MPDGCTRL0)
Supported Mode Of Operations:
For Channel 0: DDR3_x16, DDR3_x32, DDR3_x64
For Channel 1: DDR3_x64

Andy

[Yuri]

Hello,

  Generally it may be recommended to use the "i.MX6/7 DDR Stress Test

Tool V2.52".

< https://community.freescale.com/docs/DOC-105652 >

Nevertheless, please look at my comments below.

1., 4.

  ZQ control should be programmed for both channels (0 and 1) separately.

2., 3.

  And ZQ calibration should be provided for both channels and both CSs.

5.

  No need for write leveling calibration for LPDDR2.

6.

  No need for DQS calibration for LPDDR2.

Have a great day,
Yuri

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[AndyHo]

Hi Yuri,

Thank you for the answer,

1.We use Mx6DQSDL LPDDR2 Script Aid V0.04 to generate script, we decide to use ddr stress tester 1.0.3 for LPDDR2 2x32 because the calibration result of V2.51 can not boot, I will try to use v2.52, but which version of LPDDR2 script aid should I use for V2.52?

2016/4/28: we have tested the 2.52, the calibration result pass, but usually caused exception during loading kernel, we found LPDDR2 Script Aid V0.04 will generate strange parameters: like BI_ON =1....etc.

2.Could NXP provide 2.52 ddr-test-uboot-jtag-mx6dq source?

3.We have found a fine tuned calibration value ( using ddr stress test ) for most of boards, but still failed on few boards, does it means we may need to find another calibration results for those boards? or give them up? if there are more then one calibration values, how to switch them in runrime?

4.MMDC1 ZQ is controlled by MMDC0, please provide more detail about "separately" ZQ calibration:

   Because MMDC1 ZQ is controlled by MMDC0, the ZQ test result is stored in ZQ_HW_PD_RES and ZQ_HW_PU_RES of MMDCx_MPZQHWCTRL, my test result shows there is no MMDC1 ZQ result, is it possible to perform ZQ separately since MMDC1_MPZQHWCTRL is "RESERVED"? or reference manual is wrong? I think I should be able to see the ZQ result in MMDC1_MPZQHWCTRL? or the result of MMDC1 are shared with MMDC0_MPZQHWCTRL?

MMDCx_MPZQHWCTRL ( from refernce manual)

Supported Mode Of Operations:

For Channel 0: All

For Channel 1: This register is reserved for channel 1. Channel 1 ZQ is also controlled by MMDC0_MPZQHWCTRL.

My test result ( please note that I have tried to trigger MMDC1 ZQ_HW_FOR)

MMDC0 ZQ_HW_PD_RES/ZQ_HW_PU_RES are 0x18 and 0x16

MMDC1 ZQ_HW_PD_RES/ZQ_HW_PU_RES are 0x00

5. Which chip select corresponding to MPRDDLCTL and MPWRDLCTL of MMDC?

   Before perform read/write calibration, you must assign CALIB_PER_CS in MMDCx_MDMISC to assign which cs that Calibration is targetted to, and the result is stored in MPRDDLCTL and MPWRDLCTL of each MMDC, does it means only one chip of each MMDC can be calibration? In LPDDR2 2x32 mode, it's possible 4 cs connect to 4 memories chips, are you sure both cs0 and cs1 of each mmdc can be calibrated? one result for 2 memory chips of each channel? if so , why we need to assign the target cs?

Thank you.

[Yuri · Accepted solution]

Hello,

1.

  Please look at the following regarding LPDDR2 tools.

https://community.freescale.com/docs/DOC-105966

2.

  DDR stress test sources are not provided, sorry.

3.

  We do not have recommendations regarding real time changing of

DRAM settings. I expect it makes sense to use calibration during boot.

4.

  “The Reference manual incorrectly states that ZQ control for both channels are controlled by the Channel 0 register. The Correct statement is that the ZQ control should be programmed both channels (0 and 1) and will be corrected [hope] in the next RM release.”

5.

  Please follow AN4467 (Rev. 2, 03/2015), section 5 (Calibration and Chip Selects).

Regards,

Yuri.

[AndyHo]

Hi Yuri,

Thank you for the answer.

We are using imx6Q , is the i.MX6DL LPDDR2 Register Programming Aid for imx6q? if not, where is the right one?

Andy

[Yuri]

Sorry, the following is i.MX6D/Q link

i.MX6DQ LPDDR2 Register Programming Aid

Regards,

Yuri.