I'm trying to perform high-resolution PWM pulse generation when the pulse high width (1.5 ms) is relatively short (and of more significance) compared to the overall PWM period (~25 ms). To do this, I have:
- set up a PIT timer with a 25 ms period
- set up a TPM timer in edge-aligned PWM mode running at 400 Hz and a duty cycle of 60%
- enabled StartOnTrigger and StopOnOverflow on the TPM channel, and set the PIT timer overflow as the trigger source
What I expected to see was that when the PIT timer overflowed, this would trigger the TPM to start counting up, and the output from the TPM timer would:
1) go high initially
2) stay high for the duration of the 60% ON duty cycle
3) then go low during the 40% OFF duty part of the cycle
4) and remain low when the TPM overflows, until the next PIT trigger occurs.
What I am seeing is ok for steps 1, 2, and 3, but when the TPM overflows, the PWM output goes high and remains high until the next PIT trigger occurs. I haven't found anything in the reference manual to describe how the PWM channel output value should behave when overflow occurs and StopOnOverflow is enabled. It seems (although it is a bit of a guess by me) as if the TPM overflow causes the counter to stop (as intended), but also causes the counter value to reset to zero and the PWM output to go high in anticipation of the PWM operation continuing some time in the future.
Is there any way to clear the TPM PWM output value when a StopOnOverflow event occurs ? I considered using the TPM overflow interrupt to force the output low, but I haven't been able to find a register to write to for the TPM channel output value.
I can post code snippets and/or logic analyser screenshots if it helps.
At this stage, my workaround is to revert to a conventional PWM approach without a PIT trigger, and just accept that I will lose a few bits of resolution on the width of the high pulse. I have seen this post which suggests what I am asking is not possible with a KL17Z, but I would really like to get the above approach working if possible.