First off, let me refer to our previous thread on this topic:
In the thread, thanks to the excellent help of Jiri Kotzian , we eventually find that the differential clocks have been swapped on our board.
We have since made a new board (still using the IS43LD16640A LPPDDR2) where the issue have been fixed, but alas still no cigar.
Our current DRAM config has been reworked based on the example configuration attached to the following thread:
(File, hereby referred to as "Golden")
Our test SW run from INTRAM, and contains a collection of memory tests. Our primary test follows the principals described here:
Two days ago, the tests passed on one board multiple times. The test also passed after cycling power multiple times. Other heavier tests also passed, and the DRAM config. was assume functional until the tests was run on another identical board using the same config. and failed.
We then tried to load SW into the DRAM on the functional card using the same config. This also failed.
After experimenting with the config on both boards, we eventually reached a state where no tests passed on any of the boards, even using the config. which had appeared previously functional.
We then devised a new simple tests where we simple memset(...) 1kB in the start of the DRAM, and promptly read it back, counting any errors. Test success is defined to be a run with no errors. We observed on both boards that the test failed once, but then succeed every time after that. The original tests still fail at this point.
During our rework, we found the following inconsistencies between "Golden" and the Vybrid Reference Manual (RM):
DDRMC_CR12.CASLAT_LIN : RM specifies offset at 1, but "Golden" indicates 0
DDRMC_CR34 : The RM list this field in a reserved area. "Golden" still does a write here.
DDRMC_CR38 : The RM list this register as reserved, but "Golden" still writes to it
DDRMC_CR72.ZQCS_ROTATE : RM defines val=1 as reserved, but "Golden" sets this value anyway
DDRMC_CR76.CS_EN : RM specifies val=1 as reserved. "Golden" still uses this value.
DDRMC_CR76.W2R_SPLT_EN : RM specifies val=1 as reserved. "Golden" still uses this value.
DDRMC_CR78.BUR_ON_FLY_BIT : RM specifies val=0xc as not support in lpddr2 mode. This is however the recommended value for DDR3-mode
DDRMC_CR79.CTLUPD_AREF : RM specifies this feature as "not supported by PHY", hence val=1 is reserved. "Golden" still enables it.
DDRMC_CR87.ODT_RD_MAPCS0 : DDR3 specific option (ref. RM), but "Golden" still enables it.
DDRMC_CR87.ODT_WR_MAPCS0 : DDR3 specific option (ref. RM), but "Golden" still enables it.
DDRMC_CR125 : RM specifies this as a read-only/reserved register. "Golden" still writes to it.
DDRMC_CR131 : RM specifies this as a read-only/reserved register. "Golden" still writes to it.
DDRMC_PHY50 : RM list this area as reserved, but "Golden" still writes to it.
As with other threads on Vybrid LPDDR2 configuration, there seem to be some mentions of "magic" registers, registers which are listed as read only/reserved/DDR3 only/No meaning in the RM, but still are written to. From these threads it has also become apparent that NXP employees have access to some more detailed information on the subject than what is available in the RM. This information seem to even contradict the RM at some points.
Any help to offer on the topic of Vybrid LPDDR2 configuration would be (greatly) appreciated.