VPU max frequency

[kristofferglemb]

Hi there,

I'm wondering about the max frequency of the VPU core in iMX6DQ.

The reference manual states that the VPU has two clocks, aclk with max 266 MHz and cclk with max 266 or 352 MHz. Both seems to be driven from vpu_axi_clk_root, so how can I clock the VPU at 352 MHz?

It is also written that 352 MHz depends on VDD_PU_CAP with a reference to "operating ranges in the datasheet", where can I find this information?

I also found this page: Video Playback Performance Evaluation on i.MX6DQ Board

Where it seems you have clocked the VPU at 382 MHz as well, how is that done?

I would like to run the VPU at a minimum of 266 MHz to be able to encode/decode 1920x1080 @ 30 fps. So I either need to  select AXI_CLK_ROOT and make it run at 266 MHz (not sure of consequences) or select 352 MHz (PLL2_PDF0).  AXI_CLK_ROOT currently runs at 198 MHz derived from MMDC_CH0 running at 396 MHz.

Please clarify.

[Yuri]

Hello,

Maximum VPU frequency is  specified in the i.MX6 Datasheets. Our BSP supports 266 MHz since
clock configuration changing  will impact several modules because of VPU parent clock. So all sub
modules, which have the same parent clock with VPU will be affected.

   Nevertheless, please look at the following :

How do you increase VPU clock on i.MX6S?

i.MX6Q: How to increase the VPU frequency?

Have a great day,
Yuri

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[kristofferglemb]

Hi Yuri,

Thanks for your answer.

However, I don't understand why when the CONFIG_MX6_VPU_352M Linux kernel option is enabled you choose to change the frequency of PLL2_PFD2 instead of selecting the PLL2_PFD0 input to the VPU clock mux? If you do the latter no parent clock frequency changes. Could you explain that?

[kristofferglemb]

So I found the "operating ranges" in the data sheet and it seems VDDPU and VDDSOC must be higher than 1225 mV to run at 352 MHz. There is also a Linux kernel option one needs to enable to run at 352 MHz, but this disables busfreq and cpu freq scaling which is unfortunate. Why is this?

Is running the VPU at 270 MHz if VDDPU=1115 mV and VDDSOC=1175 mV feasible? Because I could possibly run AXI_CLK_ROOT at 540 MHz and then divide that by 2 or run AXI_CLK_ROOT at 270 MHz.

Hope for an answer from iMX6Q clocking experts :-)