i.MX6 Dual/Quad LPDDR2(EDB8132B4PM) Dual-Channel Issue

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i.MX6 Dual/Quad LPDDR2(EDB8132B4PM) Dual-Channel Issue

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jiujinhong
Contributor IV

Hi All,

 

We need some help for imx6 LPDDR2 dual-channel bring up.

 

Now board has passed ddr2 stress test,but if integrate new DCD cfg to u-boot and generate u-boot.imx,failed to download

it to board through mfgtools.mfgtools stop in "downloading u-boot".any can give some help?

 

DDR Config:Fixed 32x2 Config,

 

EDB8132B4PM: 256 Meg x 32@

 

DDR Chip:2 chip,1GB * 2, 8banks

 

If use DDR2 1 channel config,u-boot/kernel can run successfully in DDR2 400.

 

Attachments:

 

1)DDR datasheet

2)Micron-edb8132b4pm-0.04-2ch-2cs-400M-34ohm.inc (DDR test tool init script)

3)2ch_edb8132b4pm.cfg  ==u-boot use DCD cfg

4)hw-ddr2-layout.pdf (hardware DDR layout)

5)Mx6DQSDL LPDDR2 Script Aid V0.04-Micron EDB8132B4PM.xlsx aid script

 

 

 

DDR Stress test result:

 

 

============================================

        DDR Stress Test (2.4.0)

        Build: Dec 11 2015, 11:13:38

        Freescale Semiconductor, Inc.

============================================

 

============================================

        Chip ID

CHIP ID = i.MX6 Dual/Quad (0x63)

Internal Revision = TO1.5

============================================

 

============================================

        Boot Configuration

SRC_SBMR1(0x020d8004) = 0x00100000

SRC_SBMR2(0x020d801c) = 0x20000001

============================================

 

ARM Clock set to 1GHz

 

============================================

        DDR configuration

BOOT_CFG3[5-4]: 0x01, Fixed 2X32 map.

DDR type is LPDDR2 in 2-channel mode. Show ch0 info only

Data width: 32, bank num: 8

Row size: 14, col size: 10

Both chip select CSD0 and CSD1 are used

Density per chip select: 512MB

============================================

 

Current Tempareture: 52

============================================

 

DDR Freq: 396 MHz

 

LPDDR2 2 CHANNLES

Note: Array result[] holds the DRAM test result of each byte.

      0: test pass.  1: test fail

      4 bits respresent the result of 1 byte.  

      result 0001:byte 0 fail.

      result 0011:byte 0, 1 fail.

 

Starting Read calibration...

 

Test channel 0

ABS_OFFSET=0x00000000    result[00]=0x1111

ABS_OFFSET=0x04040404    result[01]=0x1111

ABS_OFFSET=0x08080808    result[02]=0x1111

ABS_OFFSET=0x0C0C0C0C    result[03]=0x1111

ABS_OFFSET=0x10101010    result[04]=0x1011

ABS_OFFSET=0x14141414    result[05]=0x1011

ABS_OFFSET=0x18181818    result[06]=0x0000

ABS_OFFSET=0x1C1C1C1C    result[07]=0x0000

ABS_OFFSET=0x20202020    result[08]=0x0000

ABS_OFFSET=0x24242424    result[09]=0x0000

ABS_OFFSET=0x28282828    result[0A]=0x0000

ABS_OFFSET=0x2C2C2C2C    result[0B]=0x0000

ABS_OFFSET=0x30303030    result[0C]=0x0000

ABS_OFFSET=0x34343434    result[0D]=0x0000

ABS_OFFSET=0x38383838    result[0E]=0x0000

ABS_OFFSET=0x3C3C3C3C    result[0F]=0x0000

ABS_OFFSET=0x40404040    result[10]=0x0000

ABS_OFFSET=0x44444444    result[11]=0x0000

ABS_OFFSET=0x48484848    result[12]=0x0000

ABS_OFFSET=0x4C4C4C4C    result[13]=0x0000

ABS_OFFSET=0x50505050    result[14]=0x0000

ABS_OFFSET=0x54545454    result[15]=0x0000

ABS_OFFSET=0x58585858    result[16]=0x0001

ABS_OFFSET=0x5C5C5C5C    result[17]=0x0001

ABS_OFFSET=0x60606060    result[18]=0x0111

ABS_OFFSET=0x64646464    result[19]=0x0111

ABS_OFFSET=0x68686868    result[1A]=0x1111

ABS_OFFSET=0x6C6C6C6C    result[1B]=0x1111

ABS_OFFSET=0x70707070    result[1C]=0x1111

ABS_OFFSET=0x74747474    result[1D]=0x1111

ABS_OFFSET=0x78787878    result[1E]=0x1111

ABS_OFFSET=0x7C7C7C7C    result[1F]=0x1111

 

Byte 0: (0x18 - 0x54), middle value:0x36

Byte 1: (0x18 - 0x5c), middle value:0x3a

Byte 2: (0x10 - 0x5c), middle value:0x36

Byte 3: (0x18 - 0x64), middle value:0x3e

Test channel 1

ABS_OFFSET=0x00000000    result[00]=0x1111

ABS_OFFSET=0x04040404    result[01]=0x1111

ABS_OFFSET=0x08080808    result[02]=0x1111

ABS_OFFSET=0x0C0C0C0C    result[03]=0x1111

ABS_OFFSET=0x10101010    result[04]=0x1101

ABS_OFFSET=0x14141414    result[05]=0x1001

ABS_OFFSET=0x18181818    result[06]=0x1001

ABS_OFFSET=0x1C1C1C1C    result[07]=0x1000

ABS_OFFSET=0x20202020    result[08]=0x0000

ABS_OFFSET=0x24242424    result[09]=0x0000

ABS_OFFSET=0x28282828    result[0A]=0x0000

ABS_OFFSET=0x2C2C2C2C    result[0B]=0x0000

ABS_OFFSET=0x30303030    result[0C]=0x0000

ABS_OFFSET=0x34343434    result[0D]=0x0000

ABS_OFFSET=0x38383838    result[0E]=0x0000

ABS_OFFSET=0x3C3C3C3C    result[0F]=0x0000

ABS_OFFSET=0x40404040    result[10]=0x0000

ABS_OFFSET=0x44444444    result[11]=0x0000

ABS_OFFSET=0x48484848    result[12]=0x0000

ABS_OFFSET=0x4C4C4C4C    result[13]=0x0000

ABS_OFFSET=0x50505050    result[14]=0x0000

ABS_OFFSET=0x54545454    result[15]=0x0000

ABS_OFFSET=0x58585858    result[16]=0x0000

ABS_OFFSET=0x5C5C5C5C    result[17]=0x1010

ABS_OFFSET=0x60606060    result[18]=0x1110

ABS_OFFSET=0x64646464    result[19]=0x1111

ABS_OFFSET=0x68686868    result[1A]=0x1111

ABS_OFFSET=0x6C6C6C6C    result[1B]=0x1111

ABS_OFFSET=0x70707070    result[1C]=0x1111

ABS_OFFSET=0x74747474    result[1D]=0x1111

ABS_OFFSET=0x78787878    result[1E]=0x1111

ABS_OFFSET=0x7C7C7C7C    result[1F]=0x1111

 

Byte 0: (0x1c - 0x60), middle value:0x3e

Byte 1: (0x10 - 0x58), middle value:0x34

Byte 2: (0x14 - 0x5c), middle value:0x38

Byte 3: (0x20 - 0x58), middle value:0x3c

 

MMDC0 MPRDDLCTL = 0x3E363A36, MMDC1 MPRDDLCTL = 0x3C38343E

 

Starting Write calibration...

 

Test channel 0

ABS_OFFSET=0x00000000    result[00]=0x1111

ABS_OFFSET=0x04040404    result[01]=0x0011

ABS_OFFSET=0x08080808    result[02]=0x0000

ABS_OFFSET=0x0C0C0C0C    result[03]=0x0000

ABS_OFFSET=0x10101010    result[04]=0x0000

ABS_OFFSET=0x14141414    result[05]=0x0000

ABS_OFFSET=0x18181818    result[06]=0x0000

ABS_OFFSET=0x1C1C1C1C    result[07]=0x0000

ABS_OFFSET=0x20202020    result[08]=0x0000

ABS_OFFSET=0x24242424    result[09]=0x0000

ABS_OFFSET=0x28282828    result[0A]=0x0000

ABS_OFFSET=0x2C2C2C2C    result[0B]=0x0000

ABS_OFFSET=0x30303030    result[0C]=0x0000

ABS_OFFSET=0x34343434    result[0D]=0x0000

ABS_OFFSET=0x38383838    result[0E]=0x0000

ABS_OFFSET=0x3C3C3C3C    result[0F]=0x0000

ABS_OFFSET=0x40404040    result[10]=0x0000

ABS_OFFSET=0x44444444    result[11]=0x0000

ABS_OFFSET=0x48484848    result[12]=0x0000

ABS_OFFSET=0x4C4C4C4C    result[13]=0x0000

ABS_OFFSET=0x50505050    result[14]=0x0000

ABS_OFFSET=0x54545454    result[15]=0x0000

ABS_OFFSET=0x58585858    result[16]=0x0000

ABS_OFFSET=0x5C5C5C5C    result[17]=0x0000

ABS_OFFSET=0x60606060    result[18]=0x0000

ABS_OFFSET=0x64646464    result[19]=0x0000

ABS_OFFSET=0x68686868    result[1A]=0x1111

ABS_OFFSET=0x6C6C6C6C    result[1B]=0x1111

ABS_OFFSET=0x70707070    result[1C]=0x1111

ABS_OFFSET=0x74747474    result[1D]=0x1111

ABS_OFFSET=0x78787878    result[1E]=0x1111

ABS_OFFSET=0x7C7C7C7C    result[1F]=0x1111

 

Byte 0: (0x08 - 0x64), middle value:0x36

Byte 1: (0x08 - 0x64), middle value:0x36

Byte 2: (0x04 - 0x64), middle value:0x34

Byte 3: (0x04 - 0x64), middle value:0x34

Test channel 1

ABS_OFFSET=0x00000000    result[00]=0x1011

ABS_OFFSET=0x04040404    result[01]=0x1011

ABS_OFFSET=0x08080808    result[02]=0x1010

ABS_OFFSET=0x0C0C0C0C    result[03]=0x0010

ABS_OFFSET=0x10101010    result[04]=0x0000

ABS_OFFSET=0x14141414    result[05]=0x0000

ABS_OFFSET=0x18181818    result[06]=0x0000

ABS_OFFSET=0x1C1C1C1C    result[07]=0x0000

ABS_OFFSET=0x20202020    result[08]=0x0000

ABS_OFFSET=0x24242424    result[09]=0x0000

ABS_OFFSET=0x28282828    result[0A]=0x0000

ABS_OFFSET=0x2C2C2C2C    result[0B]=0x0000

ABS_OFFSET=0x30303030    result[0C]=0x0000

ABS_OFFSET=0x34343434    result[0D]=0x0000

ABS_OFFSET=0x38383838    result[0E]=0x0000

ABS_OFFSET=0x3C3C3C3C    result[0F]=0x0000

ABS_OFFSET=0x40404040    result[10]=0x0000

ABS_OFFSET=0x44444444    result[11]=0x0000

ABS_OFFSET=0x48484848    result[12]=0x0000

ABS_OFFSET=0x4C4C4C4C    result[13]=0x0000

ABS_OFFSET=0x50505050    result[14]=0x0000

ABS_OFFSET=0x54545454    result[15]=0x0100

ABS_OFFSET=0x58585858    result[16]=0x0100

ABS_OFFSET=0x5C5C5C5C    result[17]=0x0100

ABS_OFFSET=0x60606060    result[18]=0x0100

ABS_OFFSET=0x64646464    result[19]=0x0100

ABS_OFFSET=0x68686868    result[1A]=0x0111

ABS_OFFSET=0x6C6C6C6C    result[1B]=0x1111

ABS_OFFSET=0x70707070    result[1C]=0x1111

ABS_OFFSET=0x74747474    result[1D]=0x1111

ABS_OFFSET=0x78787878    result[1E]=0x1111

ABS_OFFSET=0x7C7C7C7C    result[1F]=0x1111

 

Byte 0: (0x08 - 0x64), middle value:0x36

Byte 1: (0x10 - 0x64), middle value:0x3a

Byte 2: (0x00 - 0x50), middle value:0x28

Byte 3: (0x0c - 0x68), middle value:0x3a

 

MMDC0 MPWRDLCTL = 0x34343636,MMDC1 MPWRDLCTL = 0x3A283A36

 

 

   MMDC registers updated from calibration

 

   Read calibration

   MPRDDLCTL PHY0 (0x021b0848) = 0x3E363A36

   MPRDDLCTL PHY1 (0x021b4848) = 0x3C38343E

 

   Write calibration

   MPWRDLCTL PHY0 (0x021b0850) = 0x34343636

   MPWRDLCTL PHY1 (0x021b4850) = 0x3A283A36

 

 

Success: DDR calibration completed!!!

Original Attachment has been moved to: Micron-edb8132b4pm-0.04-2ch-2cs-400M-34ohm.inc.zip

Original Attachment has been moved to: 2ch_edb8132b4pm.cfg.zip

Original Attachment has been moved to: DDR-stress-test-result.txt.zip

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jiujinhong
Contributor IV

U-Boot 2014.04 (Mar 03 2016 - 11:21:14)

                                      

CPU:   Freescale i.MX6D rev1.5 at 792 MHz

CPU:   Temperature 44 C, calibration data: 0x5554c569

Reset cause: POR                                    

Board: MX6

I2C:   ready    

DRAM:  2 GiB

MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2

MMC: no card present                       

MMC init failed    

Using default environment

                        

In:    serial

Out:   serial

Err:   serial

Found PFUZE100 deviceid=10,revid=11

MMC: no card present              

mmc1(part 0) is current device

Boot from USB for mfgtools   

Use default environment for mfgtools

Run bootcmd_mfg: run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};

Hit any key to stop autoboot:  0                                              

Unknown command 'run' - try 'help'

Unknown command 'bootz' - try 'help'

=>                    

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jiujinhong
Contributor IV

I use below tools that can load u-boot and run memory test successfully ,seems mfgtools paramer/tools issue.

GitHub - boundarydevices/imx_usb_loader: Usb loader for imx51/53/6x

ulinux@linux:~$ sudo ./imx_usb ./mfgtool-build/images/u-boot.imx

config file <./imx_usb.conf>

vid=0x066f pid=0x3780 file_name=mx23_usb_work.conf

vid=0x15a2 pid=0x004f file_name=mx28_usb_work.conf

vid=0x15a2 pid=0x0052 file_name=mx50_usb_work.conf

vid=0x15a2 pid=0x0054 file_name=mx6_usb_work.conf

vid=0x15a2 pid=0x0061 file_name=mx6_usb_work.conf

vid=0x15a2 pid=0x0063 file_name=mx6_usb_work.conf

vid=0x15a2 pid=0x0071 file_name=mx6_usb_work.conf

vid=0x15a2 pid=0x007d file_name=mx6_usb_work.conf

vid=0x15a2 pid=0x0076 file_name=mx7_usb_work.conf

vid=0x15a2 pid=0x0041 file_name=mx51_usb_work.conf

vid=0x15a2 pid=0x004e file_name=mx53_usb_work.conf

vid=0x15a2 pid=0x006a file_name=vybrid_usb_work.conf

vid=0x066f pid=0x37ff file_name=linux_gadget.conf

config file <./mx6_usb_work.conf>

parse ./mx6_usb_work.conf

15a2:0054(mx6_qsb) bConfigurationValue =1

Interface 0 claimed

HAB security state: development mode (0x56787856)

== work item

filename ./mfgtool-build/images/u-boot.imx

load_size 0 bytes

load_addr 0x00000000

dcd 1

clear_dcd 0

plug 1

jump_mode 2

jump_addr 0x00000000

== end work item

Setting boot_data_ptr to 0

main dcd length 4b0

sub dcd length 4ac

loading binary file(./mfgtool-build/images/u-boot.imx) to 177ff400, skip=0, fsize=1ac00 type=aa

<<<109568, 109568 bytes>>>

succeeded (status 0x88888888)

jumping to 0x177ff400

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Yuri
NXP Employee
NXP Employee

Hello,

  looks like, it is necessary to change DDR frequency for 400 MHz (using
DCD table for initialization),  if all timings are configured for this frequency.

how to change DDR clock of i.mx6

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
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jiujinhong
Contributor IV

Hi Yuri,

Thanks for your reply.

for DDR2 400Mhz,We have already config DCD table to make DDR to work in 400Mhz

62 DATA 4, 0x020c4018, 0x00060324  //DDR clk to 400MHz

any other comments? I am cuting U-boot to make that it can run in IRAM so that can run memtest..

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Yuri
NXP Employee
NXP Employee

Hello,

  According to section 44.4.6.2 (Self refresh and Frequency change entry/exit)

of the i.MX6 DQ Reference Manual - for clock frequency changes - it is needed
for the DDR device to enter self-refresh mode. Hardly such operations may be

implemented in the flash_header.S. Please enter request  via NXP Web
to discus it in more details.

How to submit a new question for NXP Support

Regards,

Yuri.

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