FMPLL configuration for MPC5644A

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

FMPLL configuration for MPC5644A

1,014 Views
chandrasekarkri
Contributor III

pls help anyone how to configure fmpll in mpc5644a by Fref =40 MHZ for Fsys=120MHZ

i configured but it not working in EVT board ..my configuration is

void FMPLL_config()

{

ECSM.MUDCR.R = 0x40000000; /* 1 SRAM waitstate for fsys above 98MHz */

FMPLL.ESYNCR2.R = 0x00000002;

FMPLL.ESYNCR1.R = 0xF0020024;

while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK */

FMPLL.ESYNCR2.R = 0x00000001; /* Fsys =120Mhz */

SIU.ECCR.R = 0x00001003; /* CLKOUT to /4 because of 66MHz limit */

 

}

Labels (1)
6 Replies

641 Views
chandrasekarkri
Contributor III

Hi David Tosenovjan,

Thanks..i solved it..

0 Kudos

641 Views
chandrasekarkri
Contributor III

Hi David Tosenovjan,

Thanks for your reply..i looked my board is XPC564AKIT324S uses 40MHz crystal.still it is not working..if there any jumper settings in that board for working Fmpll?

Thanks & Regards,

chandrasekar k

0 Kudos

641 Views
davidtosenovjan
NXP TechSupport
NXP TechSupport

Check jumpers J16 whether there aren't removed.

pastedImage_0.png

641 Views
chandrasekarkri
Contributor III

Hi Martin Kovar,

I tested your code in  XPC564A 324BGA MINIMODULE BOARD(MPC5644A), but board is not responding..do you have any suggestions for this..

any jumper settings in this board or anything..

Regards,

Chandrasekar K

0 Kudos

641 Views
davidtosenovjan
NXP TechSupport
NXP TechSupport

Please, pay attention to following example code, function FMPLL_init:

https://community.freescale.com/docs/DOC-101455

Code selects used board at the beginning of main function by following macros:

#define XPC564AKIT176S 0

#define XPC564AKIT208S 1

#define XPC564AKIT324S 2

/* Choose one of 3 options above according to your configuration */

#define USED_BOARD XPC564AKIT324S

Possible issues are:

- XPC564AKIT176S and XPC564AKIT208S use 8MHz crystal

- XPC564AKIT324S uses 40MHz crystal

- 1 SRAM waitstate for fsys above 98MHz

- CLKOUT frequency must be 66MHz at most

641 Views
martin_kovar
NXP Employee
NXP Employee

Hi,

try this configuration:

/* Set sysclk = 120MHz running from PLL with 40 MHz crystal reference. */

void initSysclk (void) {

      FMPLL.ESYNCR1.B.CLKCFG = 0X7;       /* Change clk to PLL normal mode from crystal */

      FMPLL.SYNCR.R = 0x22880000;                  /* Fsys =60Mhz */

      while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK  */

      FMPLL.SYNCR.R = 0x22800000;                  /* Fsys =120Mhz */

}

Regards,

Martin