Hardware vector mode for MPC5668g?

[aswinkumarr]

Hi,

I am currently working on MPC5668g, where its a dual core with two mode of INTC. In that I am working on hardware vector mode in z6 core(with 128Mhz as system clock). I need few clarifications about hardware vector mode. In this mode, when two interrupts occurs at same time or an interrupt is occurring when one ISR is getting processed, this hardware vector mode will queue the another interrupt or will ignore that corresponding interrupt if it is low priority?.

Please drop your suggestions and please share any document available for hardware vector mode in detail.

Thanks.

[martin_kovar]

Hi,

in HW vector mode you can use the same settings as in software vector mode. Interrupts could be nested (queued) or ignore. If you would lite to use nested interrupts please look at the following example:

Example MPC5566 Hardware vector mode

In the file handlers_vle.s are created prologues and epilogues which have to be used.

About HW vector mode use can also look at this application note

http://cache.freescale.com/files/32bit/doc/app_note/AN2865.pdf?fsrch=1&sr=1&pageNum=1

Another information about HW vector mode you can find in MPC5668G reference manual in section Interrupts and Interrupt Controller (chapter 9).

Regards,

Martin