In relation to my setup described in this post SAI DMA double buffer problem, i wan't to use the UART as debug channel during run time. In order to load the system as little as possible during UART transfers, I have setup the system to use the UART via the DMA via fsl_uart:_edma_driver.c
The setup is as following:
DMA UART RX ch 0 (currently not used)
DMA UART TX ch 1
DMA I2S RX Ch 2 ( Configured in loop/ double buffer mode )
DMA I2S TX Ch 3 ( Configured in loop/ double buffer mode )
DMA abitration = Fixed priority
Priorities are left with init value (0,1,2,3).
Preemption values for the different channel has been setup.
EDMA_HAL_SetChannelPreemptMode(DMA_BASE_PTR, 0, 1, 1); // cannot suspend any channel DPA=1 , Can be suspended ECP=1
EDMA_HAL_SetChannelPreemptMode(DMA_BASE_PTR, 1, 1, 1); // cannot suspend any channel DPA=1 , Can be suspended ECP=1
EDMA_HAL_SetChannelPreemptMode(DMA_BASE_PTR, 2, 0 ,0); // can suspend low prio channel DPA=0 , Cannot be suspended ECP=0
EDMA_HAL_SetChannelPreemptMode(DMA_BASE_PTR, 3, 0, 0); // can suspend low prio channel DPA=0 , Cannot be suspended ECP=0
The UART transfer is working, however it looks like the I2S DMA are not allowed to suspend the UART RX DMA until all bytes are written to the UART ( Major loop end)
The attached dump from my scope illustrates the scenario
D15 and D14 shows the is the DMA isr for the I2S RX and TX DMA. and analog ch1 is the actual UART output.
Normally I2S DMA's will issue interrupt each 5 ms.
As can be seen the I2S DMA's seems to be blocked during UART tranmission.
Any suggestion on why this happens ?