LMEM_PSCR register not existing in K65

[peterruesch]

I'm am trying to maximize flash execution performance (which is until now 30% lower than from internal SRAM with FMC Cache activated!).

AN4745 lists the following procedure on activating the LMEM cache:

1. Modify the cache region configuration in the LMEM_PCCRMR from the default values if desired.

2. Set the LMEM_PCCCR[INVW1 and INVW0] bits to configure the controller to invalidate both ways of the CODE bus

cache.

3. Set the LMEM_PCCCR[GO] bit to start the invalidate.

4. Wait for the LMEM_PCCCR[GO] bit to clear indicating the command has completed.

5. Enable the CODE bus cache by setting LMEM_PCCR[ENCACHE].

6. Set the LMEM_PSCCR[INVW1 and INVW0] bits to configure the controller to invalidate both ways of the system bus

cache.

7. Set the LMEM_PCCCR[GO] bit to start the invalidate.

8. Wait for the LMEM_PSCCR[GO] bit to clear indicating the command has completed.

9. Enable the system bus cache by setting LMEM_PSCR[ENCACHE].

But unfortunately, I can't find any sign of existence for the registers LMEM_PSCR and LMEM_PSCCR in K65.

Am I missing something?

Edit:

Seems like these registers are only available in Kinetis K70 devices since only these have the SYSTEM cache controller.

What does this missing cache controller mean for the flashe execution performance of the K65 devices ?#

I also found out, that enabling the cache in some cases reduces the flash execution performance :smileysad: so simply enabling it may slow down the application.

Is there a special Application Note regarding cache best practices on freescale?

[Hui_Ma · Accepted solution]

Hi Peter,

That's true. For K65 without the system cache, there will missing the LEME_PSCCR and LEME_PSCRMR registers as K70 has.

The Flash operation performance could be enhanced with FMC module, which feature also be described at AN4745 document.

The FMC cache and prefetch speculation buffer allow the FMC to respond to flash accesses with no added wait states in many cases. Any time the requested information is available in the cache or prefetch buffer, the FMC responds with no added wait states.

For the frequently accessed code or data in Flash range, it is a better option to to one of the SRAM blocks (preferrably SRAM_L).

Please let me know if you have more queries about FMC module and Kinetis Cache.

BTW: Unfortunately, so far there is no documents about best practices of Kinetis Cache.

Thank you for the attention.

Have a great day,
Ma Hui

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[peterruesch]

Thanks for your answer which does NOT answer my most important question.

How can I acchieve the best flash execution performance on a K65 device?

the following diagram shows the efficency (meaning looped instructions vs. needed cpu cycles) of flash code execution.

My concern is that from a specific code size, L1 cache introduces some serious disadvantages in execution performance.

the x- axis is not properly labeled. it should read from 100 looped instructions to 32k looped instructions.

maybe I'm going to open a new topic once I finish my examinations in comparison with a stm32 product which does not have L1 cache but also  flash prefetch buffer.

hope to hear from you.

[Hui_Ma]

Hi Peter,

Our Kinetis product expert supports the same issue at thread: low flash performance on K6x , so I think we could close this thread now.

Thank you for the attention.

best regards,

Ma Hui