DDR3 Adress Lenght of iMX 6q SABRE SDB

[ahmetbolu]

Hello,

After reading another thread (About layout of address and command signal in i.MX6 SABRE-AI. ), now i can understand main guideline is hardware development guide not SABRE design Because some address lenghts are beyond the limit of HDG(Hardware Design Guide). But i also have some additional questions about lenght matching:

1) What is the meaning of +-25?Is it allowed to use 975 mil 1000 mil and 1025 mil signals together in same address group? So it means 50 mil difference is allowed?

2) As we know the propogation delay of signals are different in microstrip (on top or bottom layers) with stripline(on internal layers) So our calculations shows that (for our pcb structure) the address lenght of 1000 mil signal on internal layer is equivalent to 1078 mil signal lenght of top/bottom layer. So what could be the best aproach to match these signals?:

*Match exact lenghts(without taking into acount the propogation delays)

*Match propogation delays (equivalent lenght)

3) Since some signals are not following the same structure of the address lines, do we have to taking via lenghts into considerations? Lets say an address line use one more via or one has Layer1 to Layer8 cross and one has Layer3 to Layer6. What would be the best approach?

@Thanks in advance...

[Yuri · Accepted solution]

Really, the SABRE design has been implemented before final design checklist,

and therefore we can see some discrepancy between recommendations and design.

  Generally, alas, it is hard to give reasonable advices from rules of thumb,

nevertheless, many app notes are intended to help users in design (without

simulation). Therefore, for assurance, most reliable recommendations are

provided ( and - as result - they are very hard for realization).

   Customers may follow both approaches :

- use the reference design ;

- use recommendations in the checklist.

As for Your questions :

1)
> What is the meaning of +-25? […]

  Yes, it may be difference of 50 mils between signals in group.

Sometimes the assumed middle value is specified [in the length column] :

“Match the signals ±25 mils of the value specified in the length column”

2)

> As we know the propogation delay of signals are different in microstrip […]

3)

> Since some signals are not following the same structure of the address lines, do we have to taking via lenghts into considerations?

For complex non-standard situations please use simulation technique. 

Have a great day,
Yuri

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[ahmetbolu]

Hello Yuri,

Thanks for your answers.

Dont you have any comment for the 2nd question?

For my 2nd and 3rd question i just wonder to learn the theory of it (from an experienced user). Because the simulation programs are use the same theory with no doubt.

Thanks again ... best wishes.

-Ahmet-

[Yuri]

Hello, Ahmet !

> So what could be the best aproach to match these signals?:

> *Match exact lenghts(without taking into acount the propogation delays)

> *Match propogation delays (equivalent lenght)

Theoretically - Match propogation delays, but it would be better to simalute

signal integrity.

Regards,

Yuri.

[ahmetbolu]

Dear Yuri,

Thank you very much. So match propogation delays with taking via lenght into consideration (3rd question)? right?

Best Regards.

-Ahmet-

[Yuri]

Yes.