I'm sure I'm doing something wrong here, I just don't know what it is.
I have a test KSDK + PEx project for a FRDM-K22F and I am just tight looping, toggling a single GPIO. I have set my clock configuration to 1 (maximum) and yet my output frequency is just under 780kHz. Is there something I'm missing here?
My test app is literally Create New -> FRDM-K22F -> KSDK + PEx -> add fsl_gpio -> bitbang in while loop.
With default "max speed" clock settings:
FRDM-K22F: 780kHz
FRDM-K64F: 760kHz
- In this particular case, I configured UART1 TX on PTC4 and output characters with UART_DRV_SendData(). My best guess from the smallest pulse width when sending 0x55 is 3.68MHz. Baud rate was set to max value of 7.5MHz
under mbed (just as a quick comparison)
FRDM-K64F: 640kHz
I am not intimately familiar with the K22F clock-settings; the closest I come is K20, and I do everything 'bare metal' to be in complete control. So I can't give any particular 'hints' as to your supposed factor-of-2, which I think we can trust from your numbers!
So this guy:
Confirming K22F Clock Frequency
was making a bit-banged SPI, and I showed where an IAR-chain high-optimization loop could net 16 half-word instructions per bit in&out. If your 'inner loop' can look anything like this, you should see it cycle about 20 clocks per bit (or better!). As discussed at the end of the thread, a 'dirt simple' sequence of PORTx_PTOR 'toggles' can certainly toggle at full core-clock speed.