LVDS and PWM settings on iMX6

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LVDS and PWM settings on iMX6

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yurirellosa
Contributor IV

Hello Community,

We are having issues with display and backlight.

The fb driver seems run but the penguin logo does not show and the backlight driver doesn't seem to be even called.

Below are the related device tree parts. Is there something wrong with these settings?

mxcfb1: fb@0 {

  compatible = "fsl,mxc_sdc_fb";

  disp_dev = "ldb";

  interface_pix_fmt = "RGB24";

  mode_str ="LDB-WSVGA";

  default_bpp = <16>;

  int_clk = <0>;

  late_init = <0>;

  status = "okay";

};

&ldb {

  ipu_id = <0>;

  disp_id = <0>;

  ext_ref = <1>;

  mode = "sin0";

  sec_ipu_id = <1>;

  sec_disp_id = <0>;

  status = "okay";

};

backlight {

  compatible = "pwm-backlight";

  pwms = <&pwm1 0 10000000>;

  brightness-levels = <0 4 8 16 32 64 128 248>;

  default-brightness-level = <7>;

};

&pwm1 {

  pinctrl-names = "default";

  pinctrl-0 = <&pinctrl_pwm1_1>;

  status = "okay";

};

Also I noticed with the the reference manual for i.MX 6Dual/6Quad on page 213, IPU-1 & IPU-2 have [0260_0000] and [02A0_0000] addresses respectively.

But on imx6qdl.dtsi it is like so:

ipu1: ipu@02400000 {

  compatible = "fsl,imx6q-ipu";

  reg = <0x02400000 0x400000>;

  interrupts = <0 6 0x4 0 5 0x4>;

  clocks = <&clks 130>, <&clks 131>, <&clks 132>,

  <&clks 39>, <&clks 40>,

  <&clks 135>, <&clks 136>;

  clock-names = "bus", "di0", "di1",

       "di0_sel", "di1_sel",

       "ldb_di0", "ldb_di1";

  resets = <&src 2>;

  bypass_reset = <0>;

};

The register address is at [0240_0000] should this be corrected to [0260_0000]?

Thanks,

Yuri

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yurirellosa
Contributor IV

It seems for backlight to work, I needed the CONFIG_PWM_IMX on defconfig.

Anyone have a clue what's wrong with LDB / LVDS0?

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alejandrolozan1
NXP Employee
NXP Employee

Hi,

Which BSP or kernel version are you using? Is this problem shown in one of the FSL boards or you are working with a custom one?

Regards,

Alejandro

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yurirellosa
Contributor IV

Hello

If we assume that the device tree settings is correctly written and we have the following codes below:

Kernel Boot parameter:

video=mxcfb0:dev=ldb,LDB-WSVGA,if=RGB24 ldb=sin0 fbmem=128M

LVDS GPR iomux setting in board file:

static void __init imx6q_ipad2_ldb_mux_init(void)

{

    /*

     * MX6Q SabreSD board base:

     * DI0 enabled, 24bit width, vsync active low

     *

     */

    struct regmap *gpr;

    gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");

    if (!IS_ERR(gpr)) {

        if (of_machine_is_compatible("fsl,imx6q-ipad2")){

            regmap_update_bits(gpr, IOMUXC_GPR2, 0x0F, 0x01);

            regmap_update_bits(gpr, IOMUXC_GPR2, 0xF0, 0x0A);

            regmap_update_bits(gpr, IOMUXC_GPR2, 0xF00, 0x06);

        }

        else {

        pr_err("%s(): failed to find fsl,imx6q-ipad2 regmap\n", __func__);

        }

    } else {

        pr_err("%s(): failed to find fsl,imx6q-iomux-gpr regmap\n",

               __func__);

    }

}

Are we still missing anything to set LVDS and the graphics driver?

Best Regards

Yuri

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yurirellosa
Contributor IV

We have made the display work by the following changes on the device tree

&cpu0 {

    pu-supply = <&reg_pu>; /* use pu_dummy if VDDSOC share with VDDPU */

};

&gpc {

    pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */

};

&gpu {

    pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */

};

&vpu {

    pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */

};

We got the idea from this thread --> kernel hangs or fails to allocate CMA in galcore with i.MX Solo Sabre

From the sabresd reference device tree it was <&pu_dummy>. When we were setting this up I asked the hardware designer of the relation with VDDSOC and VDDPU.

He told me that VDDSOC generates VVDPU and are almost the same. So I interpreted this as VDDSOC "sharing with" VDDPU and retained the <&pu_dummy> settings.

Was it just my misunderstanding of the pu-supply comment? (use pu_dummy if VDDSOC share with VDDPU)

It maybe working now but we would like to make sure if these are the right settings.

Any advice would be really helpful.

Best Regards

Yuri

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ivannikolaenko
Contributor IV

Hello, Yuri,

We have the same problem.

Forgive me, but I don't quite understand, did you change "reg_pu->pu_dummy" or vice versa?

Best Regards,

Ivan.

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yurirellosa
Contributor IV

Hello Ivan,

Sorry for the very late reply, but were you able to solve your problem?

As to your question we changed "pu_dummy" -> "reg_pu".

Best Regards,

Yuri

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ivannikolaenko
Contributor IV

Hello, Yuri.

Thank You for your responce.

I have my LVDS working - that was hardware issue.

I didn't changed pu-supply at all

Best Regards,

Ivan

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yurirellosa
Contributor IV

Hello Alejandro

Sorry I forgot to put in those information.

I am working on a custom board based on imx6q-sabresd.

The versions Yocto1.7.1, Linux branch imx_3.10.17_1.0.0_ga, u-boot-flsc 2014.10

The LCD display is connected to LVDS0 and that should be getting data from IPU1.

Best Regards

Yuri

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