Low power demo for DDR3 (TWRVF65GS10)

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Low power demo for DDR3 (TWRVF65GS10)

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ayazshahid
Contributor I

Hi,

I'm trying to get DDR3 in self-refresh and power down modes. I've looked at another discussion thread which was very helpful but my data in SDRAM gets corrupted at times when I do a disable/enable cycle on the PLL (with self-refresh enabled).

I think I might be missing something along the way, it looks like there's a demo available for low power mode called "Vybrid Low Power Demo Code". How can I get access to that demo?

Thanks!

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falstaff
Senior Contributor I

Hi Ayaz,

In case it is a PLL issue, I used a loop to wait for the PLL LOCK bit. With that, I did not had to add any arbitrary delays. Something which I missed in the list I wrote in the DDR3 self-refresh entry/exit sequence post is IOMUX: Store IOMUX on suspend and restore all DDR pad settings before starting to use the memory.

Also, I suggest to connect a oscilloscope on DDR_CKE/DDR_RESET early on. There is this hardware state issue as well as missconfigured software which might cause unwanted reset. The Reset signal needs to be unchange between the whole entry/exit sequence.

--

Stefan

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naoumgitnik
Senior Contributor V

Dear Ayaz,

While discussing a similar issue some time ago with my customer-support colleagues, we came to a conclusion that PLLs need time to "warm up", i.e. need some time after the "Enable" command to start operating properly; do you provide such a delay, please?

Different PLLs need different delay durations, so quite likely you will have to experiment a little with a specific PLL.

Regards, Naoum Gitnik.

[cedricatmentor]

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ayazshahid
Contributor I

Hey Naoum,

I'm executing a few hundred NOPs in a loop to wait arbitrarily for PLL to get locked properly, I don't think its a PLL locking issue though. I think I'm missing something in the sequence that's why I wanted to have a look at the demo source/instructions.

I have two use cases a) to get DDRMC in self-refresh. b) to turn off DDRMC.

My code is running our of SRAM but SDRAM is initialized and accessible at the start of my system so I've placed a marker (say 0xdeadbeef) at a valid location in SDRAM. My expectation is that I should be able to read the same data back after I gate off DDRMC clocks while DDRMC is in self-refresh and then re-enable clocks and take it out of self-refresh. Alternatively, the marker should not be present when I gate off the DDRMC clocks without self refresh. I'm also monitoring power consumption using Monsoon Power Monitor.

Here's what I'm doing

  1. Write 0xA to LP_CMD and wait for the completion status. {no change in power consumption}
  2. Gate off clocks to DDRMC CCM_CCGR6[CG110] set to 0. {Power consumption dips at this stage.}
  3. Clear the IOMUX pads for DDRMC to further reduce the power consumption footprint. DDRMC is already in SR mode so I expect it to keep refreshing its data {Power consumption dips further down}
  4. Execute a bunch of instructions to simulate running with this power profile
  5. Redo the IOMUX settings for DDRMC {Power consumption jumps up.}
  6. Re-enable CCM_CCGR6[CG110] to supply clock to DDRMC. {Power consumption jumps up again}
  7. Execute a few hundred NOPs to wait for the clock to get stable. (This was done after your post, let me know if this should be done in a more streamlined way)
  8. Exit SR mode by writing 0x9 to LP_CMD and wait for completion status. {no change in power consumption}

At this point, if I access the memory location that I updated before going into SR mode, it shows corrupted version of the data. What am I missing?

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naoumgitnik
Senior Contributor V

Dear Ayaz,


Please, clarify if you are using one of the LPStop modes. If so, what TWRVF65GS10 revision are you using? - Rev.H has 10K pull resistors on the DDR_CKE (pull-down) and DDR_RESET (pull-up) lines that Rev.G does not. They are needed if DDR3 Self-Refresh required when Vybrid in LPStop modes ("Don't care" for other Vybrid's modes), since in these modes the DDR controller's pins go "high-impedance".

Even if you do not, does your "Clear the IOMUX pads for DDRMC" mean you make them "high-impedance"? If so, the same resistors are required for DDR3 Self-Refresh to store its data.

Sincerely, Naoum Gitnik.

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ayazshahid
Contributor I

Hey Naoum,

I am not using LPStop modes, I'm trying to turn off DDR3 only at specific points in my program and/or put it in self refresh to reduce the power consumption footprint.

By clearing the IOMUX, I mean that I restore them to their *reset* state before they were configured for DDRMC.

I was using a Rev G3 board earlier and have switched to Rev G board today. Surprisingly, the data gets corrupted only when I follow the sequence I've mentioned above and enter the self-refresh mode. Data is retained if I gate off the PLL and reset IOMUX settings *without* entering self-refresh mode.

When you say *same* resistors are required for DDR3 self-refresh, do you mean all the resistors? Is there a list of muxes that I can clear/reset? You also mentioned that you've discussed this issue before with your colleagues, can you point me to correct instructions for entering/exiting self-refresh and powering off the DDR3 altogether? I still feel that I'm missing a beat somewhere in between these instructions as these instructions are sparsely gathered from different threads etc. instead of a single document/source.

Thanks!

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naoumgitnik
Senior Contributor V

Dear Ayaz,

Before we proceed further, may you, please, take a look at the comment on the schematic sheet 10 (attached) and try to install the 2 resistors mentioned to see if it helps? If the issue persists, I will refer you to the Freescale FAE who developed the DDR3 self-refresh code last year (but without powering the DDR3 memory off, just controlling its Reset and SKE signals).

BTW, there is no difference in the DDR3 block of the design between Rev G3 and Rev G, only some component values in some other blocks, so they are supposed to behave identically in your case.

Regards, Naoum Gitnik.

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ayazshahid
Contributor I

Thanks Naoum, I'll get our hardware expert to install the two 10K resistors mentioned in *pink* comment box tomorrow.

We are really tight on schedule at the moment so would it be possible for you to get the ball rolling on sharing the reference code with me too? If installing resistances doesn't work, I'll have to wait for one more day to get the reference code from you because of our time zone differences.

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naoumgitnik
Senior Contributor V

Dear shigenobukatagiri-b39676,

I doubt the DDR3 Self-Refresh code is company-confidential; if so, may you provide the latest code version for Ayaz in this thread, please?

Thanks in advance, Naoum Gitnik.

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shigenobukatagi
NXP Employee
NXP Employee

Naoum,

I have reviewed my sample code, but I validated only recoverying from LPSTOP mode which needs re-initialize whole DDR controller. I don't think it is Ayaz wants.

Ayaz,

As Naoum mentioned, pull down resistor for DDR_CKE and pull up resistor for DDR_RESET are MUST have components for self refresh mode since Vybrid cannot keep these I/O state. Please try this first and let me know the status.

Best Regards,

Shigenobu

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ayazshahid
Contributor I

Shigenobu/Naoum,

Looks like we've got a Rev H. board in another off-shore office. We've decided to get that board shipped to us instead of modifying the ones that we've got locally. Lets put this on hold for a bit while we get the board shipped to us. I'll get back to you guys once I've run my code on the Rev H. board.

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naoumgitnik
Senior Contributor V

Dear Ayaz,

The Rev H board's power management section differs from that of all the Rev G ones', due to that its SD card image is different (but supplied with the board). If it anyhow impacts your application, it still might make sense to install 2 resistors onto the the Rev G one to keep using your code.

Sincerely, Naoum Gitnik.

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ayazshahid
Contributor I

Hey Naoum,

Thanks for the heads up! I think we should be okay there with the Rev H. board but I'll keep this in mind in case something out of the ordinary happens.         

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cedricatmentor
Contributor III

Hello karinavalencia, can you have someone look into this case?

Thanks

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