Workaround of ERR004307

[ko-hey]

Hi all Please let me confirm the workaround of ERR004307. I'll plan to use DDR3, USB_HSIC and ENET together time in my products. In the workaround of ERR004307, it was described that if we use those I/O interfaces, we should configure the DDR_INPUT bit for MIPI_HSI, USB_HSIC, and ENET to "0".The below is my understandig, is it correct? The DDR_INPUT bit for MIPI_HSI, USB_HSIC, and ENET is configure to "0". The DDR_INPUT bit for DDR3, LPDDR2 is configure to "1". http://cache.freescale.com/files/32bit/doc/errata/IMX6SDLCE.pdf Best Regards,

[igorpadykov · Accepted solution]

Hi ko-hey

yes this is correct as described in

IOMUX/DCD DRAM configuration confusion...

In general any option is allowed 0 or 1, based on DDR tests.

Best regards

igor

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[ko-hey]

Hi Igor

Thank you for your quick response!

ko-hey

[ko-hey]

Hi Igor

I have an additional question.

Is this workaround applied only for differential signals?

So that means I don't have to concern about single-ended signal.

Is it correct?

ko-hey

[igorpadykov]

Hi ko-hey

it does not depends on type of signals:

erratum refers to group of modules : DDR3, USB_HSIC and ENET -

since these I/O interfaces do not have a common voltage, configuring more than

two I/O interfaces to DDR input mode might not work.

Best regards

igor

[ko-hey]

Igor

Thank you for quick reply!

I understood.

ko-hey