MX28 with Micron DDR2, MT47H32M16

[Alankar]

Hello,

i am facing issues in initializing and accessing Micron DDR2 ram on my custom MX28 hardware, i get data abort, r14_abt on debug port, description as follows

I am trying to bring up our custom board with MX28 processor and Micron MT47H32M16HR-25E:G, We do not use any OS as linux or Windows on our hardware, we do have our own operating system which we will port for this custom hardware.

As a first step in porting i am doing evaluation of each peripheral on our custom board, till now Debug UART and Application UARTs are working well on my hardware, i have written stand alone codes which i download to internal RAM using sb_loader and can execute the code

For DDR2, i have taken reference of code from obds to initialize and read/write to DDR2, i also have MX28 EVK to test my code, the code i written for DDR2 evaluation works well on MX28 EVK which has Winbond W971GG6JB-25 on it.

Differences in Winbond and Micron are as follows

column size and row size is same, all the timing parameters are same, micron is 4 bank device, winbond is 8 bank

so i have modified only HW)DRAM_CTRL31 register value, rest of the values i kept same as from obds i got from iMX community

i have attached txt file with CPU clock and DDR initialization code

when i try to execute this code, it freezes and i get "Data Abort r14_abt : 0x000004C0" on DEBUG port, the value after r14_abt changes if i do any modifications in initialization values, but its not working

i have also attached design page for hardware design for CPU and DDR2

Please help

Original Attachment has been moved to: MX28_CPUClk_DDR2Init.c.zip

[Yuri]

Please let me know :

1) have You used the memory tool, linked below, to get optimal settings for Your SDRAM ?

Board_bring-up_and_DDR_initialization_tools :

https://community.freescale.com/docs/DOC-1455

2) It is possible to check memory via a JTAG debugger to see how data are written / read to / from

memory ?

You may try the memory test, provided in Community.

https://community.freescale.com/message/375263#375263

https://community.freescale.com/servlet/JiveServlet/download/375692-270338/mem_test.7z.zip

Have a great day,
Yuri

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[Alankar]

Hello Yuri,

thanks for your reply

i have followed these sheets to get the optimal settings, and also tried modifying different timing parameters with no success...

Actually i have written my DDR and CPU initialization code by referring to mem_test code from the second link, my code runs well on EVK but EVK has Winbond DDR2 with different configuration. i have modified these config registers to match Micron DDR2 parameters but its not working :smileysad:

i have also verified my schematic design and PCB layout for connections of CPU to DDR2, One thing i found was the trace length of EMI_DDR_OPEN + EMI_DDR_OPEN_FB is lesser than of EMI_CLK + EMI_DQS0 by around 7-8 millimeters on my PCB layout. Does this make this much of difference that DDR2 will not work at all

Also about the sb file in mem_test program does not execute it halts printing "si" only first two characters

actually i have JTAG interface on my CPU board but i dont have JTAG hardware, we generally dont use JTAG :smileysad:

[Yuri]

   Generally, the trace length has to be the sum of CLK+ DATA as it is used by the DRAM controller to estimate the delay of the DRAM signals.

I expect the mentioned signals (OPEN and OPEN_FB) are used for automatic delay calibration in auto configure mode, described in section 14.7.9 (Digital DLL and the Delay-Line) of the Reference Manual. In the same time, basically it is possible to use bypass mode, or manual configure mode, for example please look at section 14.8.82 DRAM Control Register 87 (HW_DRAM_CTL87).

Have a great day,
Yuri

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