Are there sys clk vs QSPI clock restrictions? Perhaps sys clk or bus clock has to be higher than QSPI clock? I'm asking because my code hangs when booting in XIP mode at 60MHz QSPI clock. It worked OK at 18MHz. After some debugging I found that the problem is not too slow QSPI memory. At boot time I need to reconfigure core and other clocks. To reconfigure core clock I need to switch SYS_CLK_SEL from PLL_PFD clock (default setting out of boot ROM) to fast clock (crystal oscillator clock). And this is exactly where A5 core runs away. And this is why I wonder about QSPI vs SYS clk clock restrictions or how to properly switch from PLL_PFD clock source to fast clock source.
I found that setting QSPIn_ACCZ=1 in CCM_CGPR, which makes QSPI synchronous to SYS_CLK, helps. With QSPIn_ACCZ=1 I can switch SYS_CLK_SEL with no problem. Any comments on this? Is this the right approach?