Hi Kenji,
Thank you for your suggestions!
Adding 100pF bypass capacitors to the SWD CLK and SWD DIO lines somehow allowed the reset line to toggle for one day but the problem is back.
After additional tests I've come to conclude that there's something wrong with the custom board around the reset button. There's something causing the reset pin to "see" a sawtooth waveform at around 1.7 kHz, sometimes higher, sometimes lower. It depends on what I connect to the board or if I try to add larger bypass capacitors to supress this sawtooth "ripple". Also the ripple doesn't oscillate around 3.3 V. It oscillates between 0 V and 2.0 V. That's too large of an oscillation. The reset signal is probably oscillating in and out of the hysteresis zone of the KL46's reset input pin. It's ok to have some small ripple in this line but not with this kind of amplitude. So that tells me that changing my 10 kOhm pull up resistor will not completely solve this problem. In any case, I looked at an FRDM-KL46's reset and power signals and they look very clean. So I know this problem with the custom board can be cleaned up quite a bit.
Today I'm going to look further and more carefully into the custom board with an oscilloscope and a microscope to figure out the source of the problem. I will write back to let you know how the problem was solved.
What is the correct SWD sequence that I should see when I first click the debug button and what does this sequence mean (command by command)? Maybe this is the question I should actually be asking.
I have oscilloscope captures of a successful programming sequence for the FRDM-KL46Z board. But I don't really understand them. I have read the following documents and tutorials about SWD but I'm still not quite sure of how to apply this knowledge to analyze the SWD transfers I see for the successful programming of the FRDM-KL46Z board and the unsuccessful programming of the custom KL46 board.
Here's the documents I've read:
Serial Wire Debug and the CoreSight Debug and Trace Architecture
www.arm.com/files/pdf/Serial_Wire_Debug.pdf
NXP's Introduction to Cortex Serial Wire Debugging
http://www.lpcware.com/content/blog/introduction-cortex-serial-wire-debugging-part-one
http://www.lpcware.com/content/blog/introduction-cortex-serial-wire-debugging-part-two
http://www.lpcware.com/content/blog/introduction-cortex-serial-wire-debugging-part-three
The SWD commands I see at the beginning of the successful FRDM-KL46Z programming sequence don't seem to match the 46 cycle format mentioned in ARM's SWD document. Neither do they match the SWD unlock sequence described in NXP's SWD documentation. NXP states that these are the following steps to unlock SWD:
1) The Host needs to switch the target from JTAG to SWD mode by clocking 0xE79E onto SWDCLK/SWDIO
2) SWD connection sequence- clock out more than 50 binary 1s
3) Must read the Debug Port IDCODE register (address 0)
4) Turn on Debug Port by settings bits 28 and 30 at DP address 4
5) Write AP select (debug port address 8) to 0xF0 (to prep for AP read of 0xFC)
6) Unlock Access Port by reading AP ID register (AP address 0xFC)
If the FRDM-KL46Z's successful SWD programming sequence does not match the SWD documentation then how is it possible for the Multilink programmer to successfully program the board? Is it the case that Freescale and P&E Micro have implemented a custom or proprietary initialization sequence?
Here's the first burst sequence I see when I try to program the FRDM-K46Z board:
Zooming in into the first burst:
Zooming in even more on the section right after the reset is asserted:
Thanks in advance. I will keep posting any hints and discoveries in the meantime.
