Clock sources for timers (i.MX6Q SDP)

[jotes]

Hello everyone!

I have 2 questions related to clock sources on i.MX6Q SDP. I'm using L3.0.35_4.0.0_130424, CPU frequency is 996 MHz.

1) What is the frequency of the ARM private timer's clock? Is it IPG_CLK_ROOT, ½ of ARM_CLK_ROOT, or maybe something else?

2) How to set the clock input source for EPIT to ipq_clk (Peripheral clock)? According to i.MX 6Dual/6Quad Applications Processor Reference Manual it should be done by setting bit 24 in EPITx_CR register. But as I observed, EPIT starts only when CLKSRC is set to Low-frequency reference clock (bits 24 and 25 are set).

Thanks!

[jotes]

Thank you both for your help!

Yongcai,

1) You mean ½ of ARM_CLK_ROOT frequency? If yes, it should be 498 MHz, but as I observed it is only about 68 – 69 MHz.

2) You were right, I didn't enable the clock.

[AnsonHuang]

How do you observe the local timers's freq? As local timer is system tick timer, so it is modified very frequently due to kernel scheduler, so if you just read its counter, please be aware that normally, it will be reset in several ms. So, you can try a kernel bootup with global timer, then enable local timer manually to observe its freq. Just add "nosmp" in the uboot command line, system will boot up with single core and gpt timer. Then enable localtimer manually.

[jotes]

I work with Linux on CPU0, then I enable CPU1 and configure local timer to generate the tick interrupt. Then I measure time between interrupts. I have time measured as well as value which is written to Private Timer Load Register, so I can count clock frequency.

[AnsonHuang]

Sorry, I didn't have environment to test it and give you the answer, but I am pretty sure that local timer's freq is 1/2 of ARM freq, as when ARM freq change, we need to update localtimer's freq too. And the whole system tick is based on localtimer's freq.

Maybe you can try like this, just enable local timer and set its load value to highest(assume it is counting down), then read its count, after 10 seconds(from your watch) later, read again, compare these two counts and divided by 10, you will get its freq.

[y_l]

Hi,

During wait mode in imx6 design, the arm clock will be gated and thus the local timer losts its signal. With this, system tick will be stop. During boot up (in single thread mode), when Sleep() routine is being called, the processor enters wait mode and thus the system tick stop functioning. This causes the processor never wake up as there is no interrupt being triggered.

1. If this is the case, shall we replace with another timer which works during wait mode for system tick? (If yes, what is your recommended timer?)

2. Do you know the reason why we use Private timer for system tick? 

Thanks!

[jotes]

Value in Private Timer Load Register: 0xFFFF.FFFF

Value in Private Timer Counter Register after 10 s: 0xD6FA.B75A

It gives: 0x2905.48A5 = 688.212.133

After dividing by 10, it gives about 69 MHz.

[AnsonHuang]

Can you dump the private timer’s control register value?

Best Regards.

Anson huang 黄勇才

Freescale Semiconductor Shanghai

上海浦东新区亮景路192号A座2楼

201203

Tel:021-28937058

[jotes]

Private Timer Control Register (0x00A0.0608):  0x0000.0001

[AnsonHuang]

I just tried it, it is ½ of ARM freq.

In uboot, I boot up with CORE0 @792MHz.

Then write 0x404521 to SRC_SCR register to enable CORE1.

Then using JTAG attach CORE1, and write 0xffffffff to 0xA00600(load register), I can see the 0xA00604(count) is set to 0xffffffff too. Then I write 0x1 to 0xA00608(control register), then run CORE1, after 10s, 0xA00604 is 0x10A84339, so the freq is (0xffffffff – 0x10a84339) / 10 = 401550458 ~= 401MHz, as CORE’s freq is ~800MHz, so it is ½ of ARM freq.

Best Regards.

Anson huang 黄勇才

Freescale Semiconductor Shanghai

上海浦东新区亮景路192号A座2楼

201203

Tel:021-28937058

[jotes]

I have two boards with i.MX6Q: SABRE Platform for Smart Devices Based and Sabre Lite. Since with both of them I get similar results, I guess there is something I am doing wrong. Is there any additional clock setting for this timer? I configure only two registers:

- Private Timer Load Register

- Private Timer Control Register

and apart from 'Prescaler' bits there is nothing that can change clock frequency.

[AnsonHuang]

there is no selection or additional setting for

local timer setting.

I guess you need to pay attention for the local timer register read and write. As each core can only read its own local timer. I am pretty sure that my test in uboot is making sense, but it is hard for me to point out where is wrong with your platform, you need to be careful about the CPU number , as interrupt handle may be in different CPU.

Sent from Anson's iPhone

在 2013-7-11，16:18，"jotes" <admin@community.freescale.com<mailto:admin@community.freescale.com>> 写道：

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Clock sources for timers (i.MX6Q SDP)

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[jotes]

You were right, when I test it in u-boot, I get the same result as you get (~= 401MHz). However, I don't understand why the frequency is lower when Linux is up and running.

[AnsonHuang]

It must be something wrong with you measurement method or interrupt handle, you can pay more attention to them, I think. Hardware should be OK, and the clock source for localtimer is fix, can NOT be changed via software config, I think.

[jotes]

I am doing it exactly the same way, as I did before on ZedBoard from Xilinx (with 2 ARM Cortex-A9 cores). And everything was ok, the frequency of the local timer was exactly half of ARM clock's frequency. This is why I do not understand why it is different on i.MX6 board.

Nevertheless, thank you very much for your help!

[AnsonHuang]

BTW, did you enable wait mode? Please check CCM clpcr register value, bit0-1, if wait mode is enabled and you config arm clock disabled in wait mode, then when enter wait mode local timer will lost its clock too, then it will stop running.

Sent from Anson's iPhone

在 2013-7-11，18:19，"jotes" <admin@community.freescale.com<mailto:admin@community.freescale.com>> 写道：

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Clock sources for timers (i.MX6Q SDP)

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[jotes]

Value in CCM_CLPCR: 0x00200038. Even when I set it to 0x00200018 (ARM clock enabled on wait mode) nothing has changed.

I tried to generate clock signal on the output pin by use of CCM_CCOSR register. What I've observed:

1) CLKO1_SEL: 0010 pll1_main_clk (this inputs has additional constant division /2)

output: ~ 398 MHz ← so it's ok (I tested it on Sabre Lite)

2) CLKO2_SEL: 01010 arm_clk_root (default)

output: ~ 66,7 MHz ← since CACRR[ARM_PODF] = 0, it should be equal to pll1_main_clk, am I right?

[AnsonHuang]

That depend on how you set the CCM_CCSR_PLL1_SW_CLK_SEL, if it is set to pll1, then yes, if it is set to step clock, then it is coming from step clock, and you need to check what freq it is for step clock. And can you tell me the CCOSR setting under your environment?

Best Regards.

Anson huang 黄勇才

Freescale Semiconductor Shanghai

上海浦东新区亮景路192号A座2楼

201203

Tel:021-28937058

[jotes]

CCM_CCSR[pll1_sw_clk_sel] = 0 ← pll1_main_clk(default)

CCM_CCOSR = 0x10A0100 ← arm_clk_root

CCM_CCOSR = 0x82 ← pll1_main_clk / 2

[AnsonHuang]

This setting is correct.

But I think there must be something wrong with your kernel setting or measurement, can you measure this clock in uboot? As about ARM clock, I have monitored it many times, never see such result.

Best Regards.

Anson huang 黄勇才

Freescale Semiconductor Shanghai

上海浦东新区亮景路192号A座2楼

201203

Tel:021-28937058

[jotes]

In u-boot: arm_clk_root ~= 400 MHz.