Changing the i.MX?? NAND Flash Model for Windows Embedded CE 6.0

[markwilliams]

Hi,

I am currently developing a hardware platform based on the i.MX28 and looking into suitable NAND flash.

I have noticed a series of application notes for the i.MX25, i.MX35 and i.MX51 called "Changing the i.MXyy NAND Flash Model for Windows Embedded CE 6.0" which explains how to modify the flash driver for each of the i.MX ICs.

Is there an equivalent document for the i.MX28, or is the driver architecture similar to any of the above processors so I can follow the same guide?

Thanks, Mark

[Yuri · Accepted solution]

It was already discussed :

https://community.freescale.com/docs/DOC-1372

Note, it is needed to build special version of WinCE (supporting new flash) for

the MFG tool. 

"The following solution is included in the BSP that provides the workspace for

building the MfgTool Windows Embedded CE 6.0 firmware run-time image:

WINCE600\OSDesigns\iMX28-EVK-PDK1_9-UUT"

UUT is version that is intended to be loaded by the MFG tool to SDRAM of a

target system and interface with the MFG in order to get target images and write

them to SD or NAND.

It is one, located in  firmware directory :

<mfg_dir>\Profiles\MX28 WinCE Update\OS firmware\uce_ivt.sb

[markwilliams]

Thanks for the reply, I had seen those posts from Jesseg.

Both Jesseg posts on NAND analysis for the i.MX28 refer to a NAND Analysis spreadsheet to help you work out the timing parameters.

Could you please provide a link to this spreadsheet (the one on the NAND analysis post to wiki.freescale.net does not work).

Thanks, Mark

[Yuri]

Please try the enclosed

[markwilliams]

Yuri - thank you very much for the spreadsheet. I have had a look at the various timing parameters and I will add them for my NAND.

It seems that the NAND driver only needs four timing parameters in the following stucture:

typedef struct _NANDTiming

{

BYTE DataSetup;

BYTE DataHold;

BYTE AddressSetup;

BYTE DataSample;

}NANDTiming, *PNANDTiming;

The spreadsheet seems to result in TSU TDS TDH and TCYCLE. Do you know how these relate the the above structure members?

TSU is the maximum of tCLS, tCS and tALS - is this value applied to 'AddressSetup'?

TDS is the maximum of tWP and tDS - I assume this value is 'DataSetup'?

TDH is the maximum of tWH, tREH and tDH - this value must be 'DataHold'

Where is 'DataSample' calculated and what does this parameter relate to with the NAND?

Thanks for your help, Mark

[Yuri]

Please look at my comments below.

1. 1.

> TSU is the maximum of tCLS, tCS and tALS - is this value applied to 'AddressSetup'?

1. Yes.
   
   
2. 2.
   > TDS is the maximum of tWP and tDS - I assume this value is 'DataSetup'?

Yes.

3.
> TDH is the maximum of tWH, tREH and tDH - this value must be 'DataHold'

Yes.

4.

> Where is 'DataSample' calculated and what does this parameter relate to with the NAND?

The DataSample relates to maximum of read or write cycle time (tWC, tRC).

5.
Also please be familiar with the following :

  https://community.freescale.com/thread/281571.pdf

[markwilliams]

Yuri,

Thank you again for your help. The link to the i/o voltage bug fix is very helpful as this may have caused me issues that would have been difficult to track down!

I will start modifying the drivers to test our Toshiba NAND with the i.MX28 development board.

Kind regards, Mark