MPC5777CEVB External SRAM test example

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MPC5777CEVB External SRAM test example

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1620773328
Contributor II

Hello,

We are using MPC5777CEVB and MPC57XXMB.

IDE : s32ds for Power Architecture

OS : Windows 10

 

Is there any External SRAM test example running on 32ds for Power Architecture?

 

Regards,

Jinus

1 Solution
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davidtosenovjan
NXP TechSupport
NXP TechSupport

I have just shared example code prepared with Design Studio. it works fine.

pastedImage_2.png

You can download it here:

Example_MPC5777C-External_SRAM-test-S32DS.Power.2017.R1 

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6 Replies
1,531 Views
1620773328
Contributor II
Hi David,
Thanks for your reply.
I tried to port the example you mentioned to s32,It does not work as expected.
IDE : S32DS for Power Architecture
OS : windows10
Project : freertos_mpc5777c example  project in S32SDK for Power Architecture
 
My steps as flow:
1. Change J4 to choose CS0
2. Config MMU Registers in file startup_MPC5777C.s
pastedImage_1.png
3.  Modify SRAM Init function
pastedImage_2.png
4. Run to check
pastedImage_3.png
It does not work as expected.
Regards,
Jinus
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davidtosenovjan
NXP TechSupport
NXP TechSupport

Could you show me MMU table sccrenshot as follows?

pastedImage_2.png

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1620773328
Contributor II

Hi David,

Thanks.

I don't know where i can find this tool. I am sorry.I only have startup_MPC5777C.S file. 

MMU configuration shows blow:

#if defined(MMU_CONFIG)
;#****************************** MMU configuration ********************************
#TLB1 = internal flash @ 0x0000_0000, VLE
e_lis r3,0x1001
mtspr 624,r3
e_lis r3,0xC000
e_or2i r3,0x0700
mtspr 625,r3
e_lis r3,0x0000
e_or2i r3,0x0020
mtspr 626,r3
e_lis r3,0x0000
e_or2i r3,0x003F
mtspr 627,r3
msync # Synchronize in case running from flash
tlbwe
se_isync # Synchronize in case running from flash

#TLB3 = internal SRAM @ 0x4000_0000, VLE, Write-Through Cache
e_lis r3,0x1003
mtspr 624,r3
e_lis r3,0xC000
e_or2i 3,0x0480
mtspr 625,r3
e_lis r3,0x4000
e_or2i r3,0x0030
mtspr 626,r3
e_lis r3,0x4000
e_or2i r3,0x003F
mtspr 627,r3
msync # Synchronize in case running from SRAM
tlbwe
se_isync # Synchronize in case running from SRAM

#TLB0 = pbridgeB @ 0xFFE0_0000, Cache inhibited, Guarded
e_lis r3,0x1000
mtspr 624,r3
e_lis r3,0xC000
e_or2i r3,0x0580
mtspr 625,r3
e_lis r3,0xFFE0
e_or2i r3,0x000A
mtspr 626,r3
e_lis r3,0xFFE0
e_or2i r3,0x003F
mtspr 627,r3
tlbwe

#TLB2 = external bus @ 0x2000_0000, VLE
e_lis r3,0x1002
mtspr 624,r3
e_lis r3,0xC000
e_or2i r3,0x0980
mtspr 625,r3
e_lis r3,0x2000
e_or2i r3,0x0038
mtspr 626,r3
e_lis r3,0x0000
e_or2i r3,0x003F
mtspr 627,r3
tlbwe

#TLB4 = pbridgeA @ 0xC3E0_0000, Cache inhibited, Guarded
e_lis r3,0x1004
mtspr 624,r3
e_lis r3,0xC000
e_or2i r3,0x0580
mtspr 625,r3
e_lis r3,0xC3E0
e_or2i r3,0x000A
mtspr 626,r3
e_lis r3,0xC3E0
e_or2i r3,0x003F
mtspr 627,r3
tlbwe

#TLB5 = 4k stack for each core (will be locked in cache)
# (Note: located just after 512k TLB3 entry for SRAM)
e_lis r3,0x1005
mtspr 624,r3
e_lis r3,0xC000
e_or2i r3,0x0180
mtspr 625,r3
e_lis r3,0x4008
e_or2i r3,0x0000
mtspr 626,r3
e_lis r3,0x4008
e_or2i r3,0x003F
mtspr 627,r3
tlbwe

#endif

Regards,

Jinus

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1,532 Views
davidtosenovjan
NXP TechSupport
NXP TechSupport

I have just shared example code prepared with Design Studio. it works fine.

pastedImage_2.png

You can download it here:

Example_MPC5777C-External_SRAM-test-S32DS.Power.2017.R1 

1,531 Views
1620773328
Contributor II

Problem solved. Thanks very much!!

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1,531 Views
davidtosenovjan
NXP TechSupport
NXP TechSupport

Unfortunately not. But it should not be difficult to port it as the whole setting in located in main.c file.

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