Hi NXP Team,
In one of the hardware designs we are planning to establish a communication link between two IMX8MQ processors. For that we are planning to use the PCIe as the communication medium. The reason we are trying to establish a connection using PCIe is to save the PHY space in the circuit.
On the hardware front, we are planning to establish communication using as per the below diagram.
- Can you please help to verify the hardware connections and check whether this design is feasible or not from the standard point of view?
- Can we get some software reference for this method? (I have already searched the queries in this forum but not able to find the same?