MPC5746C CRC DMA

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MPC5746C CRC DMA

631 Views
cholland
Contributor V

Hi,

This is in regards to the CRC example for Example MPC5748G CRC32 GHS614 

The CRC example works fine, but I just don't understand the DMA part of the example.

I am trying to figure out what the following code snippet means. Perhaps it should be different for the 5746C?

/* Enable DMA access on Peripheral Bridges*/
AIPS_A.MPRA.B.MTR4 = 1;
AIPS_A.MPRA.B.MTW4 = 1;
AIPS_A.MPRA.B.MPL4 = 1;

AIPS_B.MPRA.B.MTR4 = 1;
AIPS_B.MPRA.B.MTW4 = 1;
AIPS_B.MPRA.B.MPL4 = 1;

"This register specifies eight identical 4-bit fields defining the access-privilege level
associated with a bus master in the device to various peripherals. The register provides
one field per bus master. Each master is assigned a logical master number. See the device
configuration information for details."

I think MTR/MTW/MPL4 is associated with Master Bus 4, which must be "Z2 core I bus" as defined in the figure.

Maybe for the 5746C, It should be M6 (DMA)? i think that would make more sense. 

Except, MTR6 is not defined.

Maybe the MPC5746C.h file is incorrect?

The Reference manual shows MTR2 as being Reserved, but that one is showing up.

/* FILE NAME: MPC5746C.h COPYRIGHT (c) Freescale 2016 *
* REVISION: 4.0.0 All Rights Reserved *

I tried altering the file MPC5746C.h and adding the other MTR bits, then changing the '4' to '6' in the above code, but it stalls, so the '4' must be correct.

I am a bit confused at this point and need some enlightenment.  Thank you,

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Altered code to a account for MTR6

typedef union AIPS_MPRA_union_tag { /* Master Privilege Register A */
vuint32_t R;
struct {
vuint32_t _unused_31:1;
vuint32_t MTR0:1; /* Master 0 Trusted For Read */
vuint32_t MTW0:1; /* Master 0 Trusted For Writes */
vuint32_t MPL0:1; /* Master 0 Privilege Level */
vuint32_t _unused_27:1;
vuint32_t MTR1:1; /* Master 1 trusted for read */
vuint32_t MTW1:1; /* Master 1 trusted for writes */
vuint32_t MPL1:1; /* Master 1 privilege level */
vuint32_t _unused_23:1;
vuint32_t MTR2:1; /* Master 2 Trusted For Read */
vuint32_t MTW2:1; /* Master 2 Trusted For Writes */
vuint32_t MPL2:1; /* Master 2 Privilege Level */
vuint32_t _unused_19:1;
vuint32_t MTR3:1; /* Master 3 Trusted For Read */
vuint32_t MTW3:1; /* Master 3 Trusted For Writes */
vuint32_t MPL3:1; /* Master 3 Privilege Level */
vuint32_t _unused_15:1;
vuint32_t MTR4:1; /* Master 4 Trusted For Read */
vuint32_t MTW4:1; /* Master 4 Trusted For Writes */
vuint32_t MPL4:1; /* Master 4 Privilege Level */
vuint32_t _unused_11:1;
vuint32_t MTR5:1; /* Master 4 Trusted For Read */
vuint32_t MTW5:1; /* Master 4 Trusted For Writes */
vuint32_t MPL5:1; /* Master 4 Privilege Level */
vuint32_t _unused_7:1;
vuint32_t MTR6:1; /* Master 4 Trusted For Read */
vuint32_t MTW6:1; /* Master 4 Trusted For Writes */
vuint32_t MPL6:1; /* Master 4 Privilege Level */
vuint32_t _unused_4:1;
vuint32_t MTR7:1; /* Master 4 Trusted For Read */
vuint32_t MTW7:1; /* Master 4 Trusted For Writes */
vuint32_t MPL7:1; /* Master 4 Privilege Level */
} B;
} AIPS_MPRA_tag;

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551 Views
lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi Chris,

it's correct for both MPC5748G and MPC5746C. It's logical master ID value, not the AXBS crossbar port number. You need to check this table:

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Regards,

Lukas