SPI NOR FLASH BOOTING ISSUE

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SPI NOR FLASH BOOTING ISSUE

851 Views
suryakanta_moha
Contributor II

Hi Team,

We are using imx6 processor and interfaced MX66L51235FZI SPI Nor flash. ECSPI3 SPI controller is used and following are lines which are connected.

  1. ECSPI3_SS0 -DISP0_DAT3.alt2
  2. ECSPI3_CLK - DISP0_DAT0.alt2
  3. ECSPI3_MOSI-DISP0_DAT1.alt2
  4. ECSPI3_MISO- DISP0_DAT2.alt2

Boot mode selected is BOOT_MODE[1:0] as 0x10 boot from internal mode option is selected.

Boot configuration pins for BOOT_CONFIG[1:4][7:0] when serial ROM and ECSPI3 controller are selected is shown below:

00110000  00000000 00000000 00001010.

With the above configuration and SPI NOR FLASH is preloaded with SPL of 1KB @ 0x400 address. When we switch on the board uboot doesn't appear we try to probe the DISPO_DAT0 (clk) line during power up we see no clock on the line. 

Could you please let us know whether our configuration is correct or not and are we missing anything?

3 Replies

745 Views
suryakanta_moha
Contributor II

Thanks for the reply.

The processor part no which we are using is  MCIMX6D7CVT08AE and the SPI NOR FLASH part no is MX66L51235FZ2I-10G sourced from Macronix.

We have referred Reference Manual document Boot chapter no 8 and section 8.5 specific for SPI NOR Flash boot configuration and set the following coniguration for BOOT PINS:

1) Boot configuration pins for BOOT_CONFIG[1:4][7:0] when serial ROM and ECSPI3 controller are selected is shown below:

            00110000  00000000 00000000 00001010.

 2) Boot mode selected is BOOT_MODE[1:0] as 0x10 boot from internal mode option is selected.

With the above configuration and SPI NOR FLASH is preloaded with SPL of 1KB @ 0x400 address. When we switch on the board uboot doesn't appear we try to probe the DISPO_DAT0 (clk) line during power up we see no clock on the line. 

Could you please let us know whether our configuration is correct or not and are we missing anything?

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745 Views
igorpadykov
NXP Employee
NXP Employee

please check with jtag that correct boot settings were loaded in SRC_SBMR1,2 register,

they are described in sect.60.7.2 SRC Boot Mode Register 1 (SRC_SBMR1).

Also had you run ddr test, if not please run it

https://community.nxp.com/docs/DOC-105652 

Best regards
igor

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745 Views
igorpadykov
NXP Employee
NXP Employee

Hi Suryakanta

what processor used in the case (full part number)?

One can start with checking Reference Manual Boot Chapter if correct

mux options (sect."ECSPI IOMUX pin configuration") were used for ecspi boot.

Best regards
igor
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