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Help loading and running bin file via JLink

Question asked by Matthew Nunez on Feb 27, 2020
Latest reply on Feb 28, 2020 by igorpadykov

Hello,

 

I am having difficulty running the ddr-test-uboot-jtag-mx6dq.bin on my custom board with 4 MT41K256M16HA-125 chips ganged off 1 CS line and each connected to 16bits of the DDR Data bus. I am using JLink commander to load the bin file via the attached jlink commander command file. The file has the copied ddr initialization commands from the helper script excel file. It is able to successfully load the bin file to memory at 0x00907000 and it verifies successfully. The wrinkle comes when I attempt to run it it with the go command. It does nothing. No change in the PC. If I step, runs the first couple instructions before becoming stuck.

Edit: The board is configured run from NOR flash at boot and has a program that is running from there on power up. I am halting the processor and doing all of this. I have also done a reset via jlink and entered all of the following instructions directly into JLink commander before loading the code with the same result.

Here is the output:

$ JLinkExe -device MCIMX6Q4 -if JTAG -speed 4000 -autoconnect 1 -CommandFile ./MX6Q_ARD_DDR3_register_programming_aid_v1.5.txt
SEGGER J-Link Commander V6.62c (Compiled Feb 21 2020 17:43:45)
DLL version V6.62c, compiled Feb 21 2020 17:43:30

 


J-Link Command File read successfully.
Processing script file...

 

Sleep(200)

 

J-Link connection not established yet but required for command.
Connecting to J-Link via USB...O.K.
Firmware: J-Link compiled Jul 30 2008 11:24:37 ARM Rev.5
Hardware version: V5.30
S/N: 10007711
OEM: IARKS
VTref=3.300V
Target connection not established yet but required for command.
Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect
JTAGConf>
Device "MCIMX6Q4" selected.

 


Connecting to target via JTAG
TotalIRLen = 13, IRPrint = 0x0101

 

**************************
WARNING: At least one of the connected devices is not JTAG compliant (IEEE Std 1149.1, 7.1.1.d, IR-cells). (NumDevices = 3, NumBitsSet = 2)

 

**************************

 

JTAG chain detection found 3 devices:
 #0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP
 #1 Id: 0x00000001, IRLen: ?, Unknown device
 #2 Id: 0x2191E01D, IRLen: ?, Unknown device
Scanning AP map to find all available APs
AP[3]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x44770001)
AP[1]: APB-AP (IDR: 0x24770002)
AP[2]: JTAG-AP (IDR: 0x14760010)
Iterating through AP map to find APB-AP to use
AP[0]: Skipped. Not an APB-AP
AP[1]: APB-AP found
ROMTbl[0][0]: CompAddr: 82141000 CID: B105900D, PID:04-003BB907 ETB
ROMTbl[0][1]: CompAddr: 82142000 CID: B105900D, PID:04-002BB906 CTI
ROMTbl[0][2]: CompAddr: 82143000 CID: B105900D, PID:04-004BB912 TPIU
ROMTbl[0][3]: CompAddr: 82144000 CID: B105900D, PID:04-001BB908 CSTF
ROMTbl[0][4]: CompAddr: 8214F000 CID: B105100D, PID:04-000BB4A9 ROM Table
ROMTbl[1][0]: CompAddr: 82150000 CID: B105900D, PID:04-000BBC09 Cortex-A9
Found Cortex-A9 r2p10
6 code breakpoints, 4 data breakpoints
Debug architecture ARMv7.0
Data endian: little
Main ID register: 0x412FC09A
I-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
System control register:
  Instruction endian: little
  Level-1 instruction cache enabled
  Level-1 data cache enabled
  MMU enabled
  Branch prediction enabled
Memory zones:
  [0]: Default (Default access mode)
  [1]: AHB-AP (AP0) (DMA like acc. in AP0 addr. space)
  [2]: APB-AP (AP1) (DMA like acc. in AP1 addr. space)
Cortex-A9 identified.
PC: (R15) = 33BFDB60, CPSR = 800001D7 (ABORT mode, ARM FIQ dis. IRQ dis.)
Current:
     R0 =80000000, R1 =00000000, R2 =0000001F, R3 =00000002
     R4 =C1646009, R5 =00000000, R6 =80000000, R7 =00000000
     R8 =00000001, R9 =00000000, R10=0000003E, R11=3B7057B8, R12=00000001
     R13=3B705754, R14=FFFFFFFF, SPSR=600001F7
USR: R8 =00000001, R9 =00000000, R10=0000003E, R11=3B7057B8, R12=00000001
     R13=3B702000, R14=00000000
FIQ: R8 =00000000, R9 =00000000, R10=00000000, R11=00000000, R12=00000000
     R13=3B70A000, R14=00000000, SPSR=2D0A0178
IRQ: R13=3B707F1C, R14=20000117, SPSR=20000117
SVC: R13=3B6FF7B4, R14=33BD6794, SPSR=C0008084
ABT: R13=3B705754, R14=FFFFFFFF, SPSR=600001F7
UND: R13=3B704000, R14=00000000, SPSR=22005050

 

Writing 00000030 -> 020BC000

 

Writing FFFFFFFF -> 020C4068

 

Writing FFFFFFFF -> 020C406C

 

Writing FFFFFFFF -> 020C4070

 

Writing FFFFFFFF -> 020C4074

 

Writing FFFFFFFF -> 020C4078

 

Writing FFFFFFFF -> 020C407C

 

Writing FFFFFFFF -> 020C4080

 

Writing FFFFFFFF -> 020C4084

 

Writing 000C0000 -> 020E0798

 

Writing 00000000 -> 020E0758

 

Writing 00000030 -> 020E0588

 

Writing 00000030 -> 020E0594

 

Writing 00000030 -> 020E056C

 

Writing 00000030 -> 020E0578

 

Writing 00000030 -> 020E074C

 

Writing 00000030 -> 020E057C

 

Writing 00000000 -> 020E058C

 

Writing 00000030 -> 020E059C

 

Writing 00000030 -> 020E05A0

 

Writing 00000030 -> 020E078C

 

Writing 00020000 -> 020E0750

 

Writing 00000030 -> 020E05A8

 

Writing 00000030 -> 020E05B0

 

Writing 00000030 -> 020E0524

 

Writing 00000030 -> 020E051C

 

Writing 00000030 -> 020E0518

 

Writing 00000030 -> 020E050C

 

Writing 00000030 -> 020E05B8

 

Writing 00000030 -> 020E05C0

 

Writing 00018200 -> 020E0534

 

Writing 00008000 -> 020E0538

 

Writing 00018200 -> 020E053C

 

Writing 00018200 -> 020E0540

 

Writing 00018200 -> 020E0544

 

Writing 00018200 -> 020E0548

 

Writing 00018200 -> 020E054C

 

Writing 00018200 -> 020E0550

 

Writing 00020000 -> 020E0774

 

Writing 00000030 -> 020E0784

 

Writing 00000030 -> 020E0788

 

Writing 00000030 -> 020E0794

 

Writing 00000030 -> 020E079C

 

Writing 00000030 -> 020E07A0

 

Writing 00000030 -> 020E07A4

 

Writing 00000030 -> 020E07A8

 

Writing 00000030 -> 020E0748

 

Writing 00000030 -> 020E05AC

 

Writing 00000030 -> 020E05B4

 

Writing 00000030 -> 020E0528

 

Writing 00000030 -> 020E0520

 

Writing 00000030 -> 020E0514

 

Writing 00000030 -> 020E0510

 

Writing 00000030 -> 020E05BC

 

Writing 00000030 -> 020E05C4

 

Writing 00008000 -> 021B001C

 

Writing A1390003 -> 021B0800

 

Writing 001F001F -> 021B080C

 

Writing 001F001F -> 021B0810

 

Writing 001F001F -> 021B480C

 

Writing 001F001F -> 021B4810

 

Writing 43260335 -> 021B083C

 

Writing 031A030B -> 021B0840

 

Writing 4323033B -> 021B483C

 

Writing 0323026F -> 021B4840

 

Writing 483D4545 -> 021B0848

 

Writing 44433E48 -> 021B4848

 

Writing 41444840 -> 021B0850

 

Writing 4835483E -> 021B4850

 

Writing 33333333 -> 021B081C

 

Writing 33333333 -> 021B0820

 

Writing 33333333 -> 021B0824

 

Writing 33333333 -> 021B0828

 

Writing 33333333 -> 021B481C

 

Writing 33333333 -> 021B4820

 

Writing 33333333 -> 021B4824

 

Writing 33333333 -> 021B4828

 

Writing 00000800 -> 021B08B8

 

Writing 00000800 -> 021B48B8

 

Writing 00020036 -> 021B0004

 

Writing 09444040 -> 021B0008

 

Writing 8A8F7955 -> 021B000C

 

Writing FF328F64 -> 021B0010

 

Writing 01FF00DB -> 021B0014

 

Writing 00001740 -> 021B0018

 

Writing 00011740 -> 021B0018

 

Writing 00008000 -> 021B001C

 

Writing 000026D2 -> 021B002C

 

Writing 008F1023 -> 021B0030

 

Writing 00000047 -> 021B0040

 

Writing 841A0000 -> 021B0000

 

Writing 04088032 -> 021B001C

 

Writing 00008033 -> 021B001C

 

Writing 00048031 -> 021B001C

 

Writing 09408030 -> 021B001C

 

Writing 04008040 -> 021B001C

 

Writing 0408803A -> 021B001C

 

Writing 0000803B -> 021B001C

 

Writing 00048039 -> 021B001C

 

Writing 09408038 -> 021B001C

 

Writing 04008048 -> 021B001C

 

Writing 00005800 -> 021B0020

 

Writing 00011117 -> 021B0818

 

Writing 00011117 -> 021B4818

 

Writing 00025576 -> 021B0004

 

Writing 00011006 -> 021B0404

 

Writing 00000000 -> 021B001C

 

Downloading file [./../../ddr-test-uboot-jtag-mx6dq.bin]...
O.K.

 


Script processing completed.

 

J-Link>go
J-Link>halt
PC: (R15) = 00907000, CPSR = 800001D7 (ABORT mode, ARM FIQ dis. IRQ dis.)
Current:
     R0 =80000000, R1 =00000000, R2 =0000001F, R3 =00000002
     R4 =C1646009, R5 =00000000, R6 =80000000, R7 =00000000
     R8 =00000001, R9 =00000000, R10=0000003E, R11=3B7057B8, R12=00000001
     R13=3B705754, R14=FFFFFFFF, SPSR=600001F7
USR: R8 =00000001, R9 =00000000, R10=0000003E, R11=3B7057B8, R12=00000001
     R13=3B702000, R14=00000000
FIQ: R8 =00000000, R9 =00000000, R10=00000000, R11=00000000, R12=00000000
     R13=3B70A000, R14=00000000, SPSR=2D0A0178
IRQ: R13=3B707F1C, R14=20000117, SPSR=20000117
SVC: R13=3B6FF7B4, R14=33BD6794, SPSR=C0008084
ABT: R13=3B705754, R14=FFFFFFFF, SPSR=600001F7
UND: R13=3B704000, R14=00000000, SPSR=22005050
J-Link>s
00907000:  18 F0 9F E5        LDR     PC, [PC, #+0x18]    ; 0x00907020
J-Link>s
00907174:  51 00 00 EB        BL      #+0x144             ; 0x009072C0
J-Link>s
009072C0:  FF 5F 2D E9        PUSH    {R0-R12,LR}
J-Link>s
009072C0:  FF 5F 2D E9        PUSH    {R0-R12,LR}
J-Link>s
009072C0:  FF 5F 2D E9        PUSH    {R0-R12,LR}
J-Link>s
009072C0:  FF 5F 2D E9        PUSH    {R0-R12,LR}
J-Link>verifybin /Users/xxx/ddr_stress_tester_uboot_v3.00/ddr-test-uboot-jtag-mx6dq.bin 907000
Loading binary file /Users/xxx/ddr_stress_tester_uboot_v3.00/ddr-test-uboot-jtag-mx6dq.bin
Reading 121880 bytes data from target memory @ 0x00907000.
Verify successful.

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