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ls1021a standalone power reset control signals (JTAG related)

Question asked by Elias Bitbaker on Dec 9, 2019
Latest reply on Dec 10, 2019 by Elias Bitbaker



I have a standalone ls1021a and instead of using CPLD to do the board bring up I used atmega328p


Please refer to my below thread as well:

1021a board bring up replace CPLD with Atmega328P 


I need help with this really important question regarding my current design:


(1) Do I have to include HRESET in my  design as I see from the AN4878:


(2) If (1) is the case What is the signalling sequence needed on the PORESET and HRESET lines of the LS1021A to properly bring it out of reset and enable it to detect the JTAG interface?
(3) Also this
By saying " to bring the processor out of reset" , under what conditions does the processor is out of reset