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1021a board bring up replace CPLD with Atmega328P

Question asked by Elias Bitbaker on Nov 24, 2019
Latest reply on Dec 12, 2019 by Elias Bitbaker

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Hi Guys,

I have a standalone ls1021a, eMMC, a Atemega328P chipset on the board and a JTAG interface. I want to bring the board up to initiates the power-on reset flow. I am trying to implement the CPLD logic into C using Atemega328P to achieve the board initialization stage.

Does any one know how many signals do I need to consider which I need to trigger them in the right sequence?

According to the QorIQ LA1021A Reference Manual.

I also have a question specifically during the POR sequence,

Do I have to give a signal to the cfg_eng_use0 or once the POR starts everything will be handled by itself.

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31 Replies

ufedor Nov 25, 2019 2:31 AM
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It is reasonable to refer to the TWR-LS1021A design documents (including CPLD source) available at:
QorIQ® LS1021A Tower® System Module | NXP

The cfg_eng_use0 has to be connected as stated in the AN4878 - QorIQ LS1021A Design Checklist, Table 8. LS1021A reset configuration signals. Also in this application note 4.3.1 Configuration signals sampled at reset it is written:
"Reset configuration signals are sampled at the negation of PORESET_B. However, there is a setup and hold time for these signals relative to the rising edge of PORESET_B, as described in the chip's data sheet."
So this is the board designer's responsibility to properly strap (by resistor) the cfg_eng_use0.

> Do I have to give a signal to the cfg_eng_use0
After PORESET_B is deasserted the pin function is IFC_WE0_B which is pure output, so it is not possible to drive the signal externally during normal operation.
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- Elias Bitbaker @ ufedor on Nov 25, 2019 8:27 AM
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  (1) "Reset configuration signals are sampled at the negation of PORESET_B" --------------------------> does negation mean the falling edge of this signal then to low?
  
  According to the data sheet Section 4.4.1 of LS1021a reference manual:
  6. External system logic negates PORESET_B after its required hold time and after
  POR configuration inputs have been valid for their required setup times.
  7. The device samples the RCW source POR configuration inputs (cfg_rcw_src[0:n])
  on deassertion of PORESET_B to determine the RCW source. Note that the POR --------------------------> does deassertion means rising edge then to high
  configuration inputs are sampled only on a PORESET_B.
  
  (2)so basically after drive the PORESET_B to high for 1ms minimum, it will start validate the POR inputs to determine the boot source, so all I need to do is to drive this pin high for 1ms high then low for amount of time after the POR configuration inputs have been valid for their required setup times then what should I do after?
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  - ufedor @ Elias Bitbaker on Nov 25, 2019 9:27 AM
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    1) PORESET_B is an active-low cignal (_B), thus:
    negation = deassertion = low->high edge
    
    2) Not correct - see 1) and refer to the POR sequence from the processor's RM.
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    - Elias Bitbaker @ ufedor on Nov 25, 2019 9:44 AM
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      so basically :
      
      4.3 Power-on reset recommendations
      Various chip functions are initialized by sampling certain signals during the assertion of PORESET_B. These power-on reset
      (POR) inputs are pulled either high or low during this period. While these pins are generally output pins during normal
      operation, they are treated as inputs while PORESET_B is asserted. When PORESET_B de-asserts, the configuration pins
      are sampled and latched into registers, and the pins then take on their normal output circuit characteristics.
      
      so by saying asserted in this case means the signal is active low?
      
      Just want to double confirm with you last time:
      
      So basically this signal is active low and then if I make it stays low for 1ms then after 4 system clocks drive it to high (the falling edge requires max 1 sys clock cycle) then it will start sampling the boot source cfg_rcw_src[0:n]?
      
      before asserting this PORESET_B signal do I need to perform a toggling event on this pin?
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      - ufedor @ Elias Bitbaker on Nov 25, 2019 9:51 AM
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        > so by saying asserted in this case means the signal is active low?
        Yes.
        
        > So basically this signal is active low and then if I make it stays low for 1ms
        > drive it to high (the falling edge requires max 1 sys clock cycle) then it will start
        > sampling the boot source cfg_rcw_src[0:n]?
        Correct - also refer to the LS1021A Data Sheet, Table 24. RESET initialization timing specifications
        
        > before asserting this PORESET_B signal do I need to perform a toggling event on this pin?
        No.
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        Elias Bitbaker @ ufedor on Nov 25, 2019 12:13 PM
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        how about the power reset control signal from the PMIC?
        is this be asserted automatically once PORESET_B is high?
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        ufedor @ Elias Bitbaker on Nov 25, 2019 9:24 PM
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        > is this be asserted automatically once PORESET_B is high?
        What do you mean?
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        Elias Bitbaker @ ufedor on Nov 26, 2019 6:18 AM
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        There is POR_B control pin coming out of the PMIC
        I am not sure if this one POR_B is the one in the CPLD por_assert
        parameter   [2:0]por_assert = 3'b101;       //POR reset
        
        (1) If so what does the pin do in terms of PORESET_B, how does POR_B relates to PORESET_B ?
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        ufedor @ Elias Bitbaker on Nov 30, 2019 1:19 AM
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        In the CPLD source:
        input por_b; //PORB of 34VR500
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        Elias Bitbaker @ ufedor on Dec 8, 2019 9:16 AM
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        would you be able to tell me should I wait for this por_b signal asserted then perform a powerest_b
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        Elias Bitbaker @ ufedor on Nov 29, 2019 12:51 PM
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        Hi ufedor,
        
        Any specific singal requirements before the ls1021a standalnoe prototype to detect the codewarrior tap via the usb interface?
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        ufedor @ Elias Bitbaker on Nov 29, 2019 9:14 PM
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        Sorry, the request is not clear.
        What does it mean "to detect the codewarrior tap via the usb interface"?
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        Elias Bitbaker @ ufedor on Nov 29, 2019 9:35 PM
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        I meant in order to flash the ls1021a standalone chip using The codewarrior tap are there any signals have to be enabled first
        
        Sent from my iPhone
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        ufedor @ Elias Bitbaker on Nov 30, 2019 1:20 AM
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        The processor has to be connected as described in the AN4878 - LS1021A Design Checklist.
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        Elias Bitbaker @ ufedor on Dec 1, 2019 1:21 PM
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        can you take a look at his regarding the JTAG/COP port is used case
        
        This is from the LS1021a data sheet below:
        
        Also this is my design below:
        
        (1)I used a resistor R88 to connect TRST and POWER RESET Line does this
        match the requirements?
        
        Also,
        (2)
        
        this graph here shows that the ALSLEEP signal goes up after the PORESET_B
        deasserted. I used my oscilloscope to check both signals I found that the
        asleep signals goes high at the point when PORESET_B goes low. Is that
        actually normal ?
        
        On Sat, Nov 30, 2019 at 12:34 AM Elias Bitbaker <elias.bitbaker@gmail.com>
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        Elias Bitbaker @ ufedor on Dec 1, 2019 2:31 PM
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        The one on the top is the POWERET_B and the bottom is the ALSLEEP signal
        the behaviour is not following what the datasheet says.
        
        On Sun, Dec 1, 2019 at 4:21 PM Elias Bitbaker <elias.bitbaker@gmail.com>
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        ufedor @ Elias Bitbaker on Dec 2, 2019 12:03 AM
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        > asleep signals goes high at the point when PORESET_B goes low
        This is OK considering that ASLEEP is tri-stated and has a pull-up.
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        Elias Bitbaker @ ufedor on Dec 2, 2019 7:13 AM
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        can you take a look at his regarding the JTAG/COP port is used case
        
        This is from the LS1021a data sheet below:
                                                                                         Figure - A
        
                                                                                                      Figure - B
        
                                                                      Figure - C
        
        (1)I used a resistor R88 to connect TRST and POWER RESET Line does this
        match the requirements as shown in Figure A? These two pins are then pulled up by a 10k resistor to Vcc_O1VDD, my design does not have HRESET_B pin.
        
        (2)So as picture shows below: why there are HRESET_B and PORESET_B on the left side what source triggers them?
        
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        ufedor @ Elias Bitbaker on Dec 2, 2019 7:19 AM
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        The R88 is OK, but you have to consider the QorIQ LS1021A Data Sheet, Table 24. RESET initialization timing specifications:
        "Maximum rise/fall time of PORESET_B is 1 SYSCLKs"
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        Elias Bitbaker @ ufedor on Dec 2, 2019 7:33 AM
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        (1)by saying that because I use c logic to implement the start up logic what I am doing is before asserting the PORESET_B, I drive it to high then low (asserted) for 50ms (tho only needs 1ms min) then I de-assert PORESET_B then I did DDR reset, PCIE reset some I/O interface enabled. How am I able to manage the rise/fall time via the C code on AVR studio IDE which I am using to flash the code into the atmega on my board
        
        (2) What is the relation between PORESET_B and TRST_B
        
        seems like HRESET_B and TRST_B has relation but TRST_B and PORESET_B does not according to the CPLD code on the TWR-LS1021A eva board:
        /CPU, DDR and peripheral devices reset
        assign poreset_b_18 = pwr_hrst_n && jtag_rst_b_18 && sw_rst_n;
        assign cpu_trst_b_18 = pwr_hrst_n && k20_trst_b_18;
        assign rst_flsh_n = pwr_hrst_n;
        assign elev_rstout = hreset_b_18;
        assign ddr_rst_b = hreset_b_18;
        assign ethphy_rst_b = hreset_b_18;
        assign rst_usbhub = hreset_b_18;
        assign hdmi_rst_b = hreset_b_18;
        assign rst_pcie_n = hreset_b_18;
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        ufedor @ Elias Bitbaker on Dec 2, 2019 8:46 AM
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        1) The question was not about the CPLD, but about the transistor which is used to assert the PORESET_B - in thia case the Data Sheet requirement can't be fulfilled.
        
        2) The question is not clear.
        assign poreset_b_18 = pwr_hrst_n && jtag_rst_b_18 && sw_rst_n;
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        Elias Bitbaker @ ufedor on Dec 2, 2019 2:24 PM
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        yeah I know
        my case I only have poreset_b_18 but no pwr_hrst_n that's why you see my R88 is connected with poreset_b_18
        
        (1)but in the CPLD logic cpu_trst_b_18 is the TRST _B right?
        
        (2) so there should be no dependence between cpu_trst_b_18 and poreset_b_18?
        In other words, if I remove the attachment of cpu_trst_b_18 to poreset_b_18 ( I meant cut off the R88 line) it won't affect anything for the JTAG connection?
        
        But according to the checklist:
        Ensure that TRST_B is asserted during power-on reset flow to ensure that the JTAG boundary logic does not
        interfere with normal chip operation. The TEST_SEL_B pin must be pulled to OV DD through a 100 Ω to 1 kΩ
        resistor.
        
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        Elias Bitbaker @ Elias Bitbaker on Dec 2, 2019 7:28 PM
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        so we measured the PORESET_B signal and we found that the rising edge is 1 us which is 100 times more than 10ns. The system clock is 100MHz, but the PORESET_B is attached
        with a npn transistor
        
        The signal 1 above is the PORESET_B
        
        So I do not think this transistor can respond that fast
        
        We want to know if
        (1) we can use Schmitt trigger to replace the transistor to achieve this rising/falling requirement as I see from the datasheet that this can make the falling and rising at 2.5ns at Vdd 3.3V
        (2) also we want know if we need use a Schmitt trigger  circuit if choose to implement the scenario (1) at the PORESET_B input of the ls1021a
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        ufedor @ Elias Bitbaker on Dec 2, 2019 8:18 PM
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        Specific schematics solution is up to the board designer considering the the Data Sheet requirements are fulfilled.
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        Elias Bitbaker @ ufedor on Dec 3, 2019 9:51 AM
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        just want to ask you if the scenario I mentioned above is possible as I want to reduce the cost by not using CPLD ? This is really important to me.
        
        Thanks
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        Elias Bitbaker @ ufedor on Dec 8, 2019 5:53 PM
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        Hi ufedor,
        
        Do I have to design a hreset_b_18 signal too? what gonna happen if I did not consider this signal on my PCB, I only have poreset_b_18 in my design consideration
        
        In other words,
        
        Does HRESET_B needs to be part of the design?
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        ufedor @ Elias Bitbaker on Dec 10, 2019 10:35 AM
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        Only PORESET_B is essential during POR sequence - refer to the QorIQ LS1021A Reference Manual, 4.4.1 Power-on reset sequence.
        HRESET_B is not needed for JTAG interface proper operation.
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        Elias Bitbaker @ ufedor on Dec 12, 2019 6:44 AM
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        We used oscilloscope to scope the signal of JTAG_RESET and PORESET_B we found this on the eva board
        
        The power reset gets triggered 3 times whenever you try to run the debug mode from the CW via JTAG interface.
        
        Do I have to trigger the same sync wave forms on my atmega328p ? remember I replaced CPLD controller with atemega328p on my device
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        Elias Bitbaker @ Elias Bitbaker on Dec 12, 2019 6:49 AM
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        Yiping Wang
        
        can you give some thoughts on this ? Thanks
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        ufedor @ Elias Bitbaker on Dec 12, 2019 6:50 AM
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        The JTAG interface must be implemented as shown in the AN4878 - LS1021A Design Checklist, Figure 32. JTAG interface connection.
        The debugger asserts nRESET several timed to establish connection.
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        Elias Bitbaker @ ufedor on Dec 12, 2019 10:19 AM
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        I understand that my only question here is do they have to match the signal synchronization like the one in the pic I shared that part of the thing I could not tell from Figure 32
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