Hi Guys,
I have a standalone ls1021a, eMMC, a Atemega328P chipset on the board and a JTAG interface. I want to bring the board up to initiates the power-on reset flow. I am trying to implement the CPLD logic into C using Atemega328P to achieve the board initialization stage.
Does any one know how many signals do I need to consider which I need to trigger them in the right sequence?
According to the QorIQ LA1021A Reference Manual.
I also have a question specifically during the POR sequence,
Do I have to give a signal to the cfg_eng_use0 or once the POR starts everything will be handled by itself.
It is reasonable to refer to the TWR-LS1021A design documents (including CPLD source) available at:
QorIQ® LS1021A Tower® System Module | NXP
The cfg_eng_use0 has to be connected as stated in the AN4878 - QorIQ LS1021A Design Checklist, Table 8. LS1021A reset configuration signals. Also in this application note 4.3.1 Configuration signals sampled at reset it is written:
"Reset configuration signals are sampled at the negation of PORESET_B. However, there is a setup and hold time for these signals relative to the rising edge of PORESET_B, as described in the chip's data sheet."
So this is the board designer's responsibility to properly strap (by resistor) the cfg_eng_use0.
> Do I have to give a signal to the cfg_eng_use0
After PORESET_B is deasserted the pin function is IFC_WE0_B which is pure output, so it is not possible to drive the signal externally during normal operation.