Hi
i try 1GB ,2 GB 3 GB is ok but, i push 4GB QDP to the evk and run the ddr tools.
*************************************************************************
MX8 DDR Stress Test V2.10
Built on Mar 5 2019 14:26:42
*************************************************************************
--Set up the MMU and enable I and D cache--
- This is the Cortex-A53 core
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug
- VMCR Check:
- ttbr0_el3: 0x91d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1122
- MMU and cache setup complete
*************************************************************************
ARM clock(CA53) rate: 800MHz
DDR Clock: 1600MHz
============================================
DDR configuration
DDR type is LPDDR4
Data width: 32, bank num: 8
Row size: 16, col size: 10
Two chip selects are used
Number of DDR controllers used on the SoC: 1
Density per chip select: 2048MB
Density per controller is: 4096MB
Total density detected on the board is: 4096MB
============================================
MX8M: Cortex-A53 is found
*************************************************************************
============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @1600Mhz...
PMU: Error: CA Training Failed.
PMU: ***** Assertion Error - terminating *****
[Result] FAILED
Why???
is it about
2.1. Design checklist table
Table 3. LPDDR4 recommendations (i.MX 8MDQLQ)
The processor does not support byte mode specified in JESD209-4B.
??????????????????????
please help
