I designed a board with imx8m and 2 chips of DDR3L, part number is mt41k256m16tw-125 AAT, which could not be calibrated with MSCALE_DDR_Tool.
I used two CS signals and two CLK signals, CS0 and CLKA(CLKA_N/CLKA_P) for one DDR3L, CS1 and CLKB(CLKB_N/CLKB_P) for anohter DDR3L。
My question is how to set the MSCALE_DDR_Tool to pass the calibration? And if electrical connection is correct? The following PDF file is part of my schemtic for your reference.