SerDes options on LS1021a

[jiye]

Hi Guys,

My linux kernel is 4.19 and I am using lsdk1906.

I am checking through the possible SerDes options for my ls1021a chipset. When I came across the data sheet 

Please see the attachment.

Currently in my RCW my protocol of SerDes is : Using SERDES1 Protocol: 48 (0x30)

(1)How am I able to know which one is the best to fit my application. I only have a wifi module attached to the pcie1 interface.

(2)Is that correct that if I choose to occupy all the lanes for pcie1 will result in the max throughput ?

which is 6GHz for each lane. But does this gonna affect more power consumption?

(3) How am I able to make the PCIe achieve 6GHz transmission rate.  

If I do not need to use the HDD  does that mean I dont need to use the SATA1 ?

OR If I do not need to use the ethernet I dont need to use the SGMII1?

[ufedor]

1) SeDes protocol (0x30) is suitable for the described use-case.

PLL2 can be disabled because SATA1 is not used.

2) Maximum data rate for the PCIe Gen2 is 5Gbps.

Greater throughput is possible only if the PCIe agent device supports x2 or x4 link widths.

The PEX power consumptions for x1, x2 and x4 configurations are provided in the QorIQ LS1021A Data Sheet.

3) Maximum data rate for the PCIe Gen2 is 5Gbps.

Please refer to the QorIQ LS1021A Reference Manual, Table 4-14. RCW field descriptions, SRDS_DIV_PEX.

[jiye]

Hi ufedor,

How can I load a default RCW file and change some of its values.

[ufedor]

This is not possible.

All RCW fields are initialized only during POR and can't be altered later.

[jiye]

Hi ufedor,

Maybe I did not clarify the question. I know it has to be done during the POR. My question is

(1)

How am I able to create a boot image which contains RCW,PBL and uboot using LSDK1906. Once this is done how am I able to change settings of the RCW and recompile back into the boot image ? This boot image is for me to burn into the eMMC

or

(2)if there is a way to just compile the RCW file directly ,how to generate this file and then change some settings and then  add it into the boot image binary

[ufedor]

Please create new Community threads for your questions.

[jiye]

Hi ufedor,

Thanks for the reply. However, what is the difference between setting 2 (x2) lanes for PCIe1 compare to that of only one (x1) lane on the Serdes interface. Does that gonna make a difference in terms of the throughput ? I know x2 is consuming more power. 

[ufedor]

Throughput can be nearly doubled if PCIe x2 is configured in the LS1021A SerDes and PCIe add-in card supports x2 link width.

[jiye]

Hi ufedor,

I have a ls1021a chipset and external eMMC. I am planning to using Code Warrior Armv7 tool to program RCW and PBL into the eMMC via JTAG. But I heard from a NXP engineer says I can not use Armv7 tool to program the eMMC. Do you have any thoughts on this?

[ufedor]

> NXP engineer says I can not use Armv7 tool to program the eMMC

This is correct.

[jiye]

then what is the correct tool to use to program the eMMC?

[ufedor]

Please create new Community question for the eMMC programming discussion.