eMMC 5.1 error-84 w/ iMX8M

[riteshpatel]

Hi,

We are working on iMX8MQ6 based custom board & able to detect 32GB eMMC 5.1 memory.

While performing read/write operation in HS400 mode, we are getting error -84. See the error logs below. 

-----Error Log-------

root@imx8mqpicoitx:~/temp#
root@imx8mqpicoitx:~/temp#
sh .@imx8mqpicoitx:~/temp# cp ../test-utility/test-scripts/verification_utility.s
root@imx8mqpicoitx:~/temp# ls
Image
fsl-imx8mq-picoitx.dtb
fsl-imx8mq-picoitx.dtb_3.0_host_gpio12_gpr_remove
fsl-imx8mq-picoitx.dtb_drive_strength_update
fsl-imx8mq-picoitx.dtb_orig
fsl-imx8mq-picoitx.dtb_with_hub
fsl-imx8mq-picoitx.dtb_wo_hub
verification_utility.sh
root@imx8mqpicoitx:~/temp# sync
[ 51.470610] mmcblk0: error -84 transferring data, sector 16490, nr 1, cmd response 0x900, card status 0x0
[ 51.655504] mmcblk0: error -84 transferring data, sector 16490, nr 1, cmd response 0x900, card status 0x0
[ 51.665170] blk_update_request: I/O error, dev mmcblk0, sector 16490
[ 51.671601] Buffer I/O error on dev mmcblk0p1, logical block 106, lost async page write
[ 51.750087] mmcblk0: error -84 transferring data, sector 16426, nr 1, cmd response 0x900, card status 0x0
[ 51.759801] blk_update_request: I/O error, dev mmcblk0, sector 16426
[ 51.766179] Buffer I/O error on dev mmcblk0p1, logical block 42, lost async page write
root@imx8mqpicoitx:~/temp#
root@imx8mqpicoitx:~/temp#

--------------------

----eMMC detection log----

root@imx8mqpicoitx:~# cat /sys/kernel/debug/mmc0/ios
clock: 200000000 Hz
actual clock: 200000000 Hz
vdd: 21 (3.3 ~ 3.4 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 3 (8 bits)
timing spec: 10 (mmc HS400)
signal voltage: 1 (1.80 V)
driver type: 0 (driver type)

----------------------------------

We referred following links:

- https://community.nxp.com/thread/377747 - Layout is verified Okay

- https://community.nxp.com/thread/360220 - We are able to detect eMMC successfully.

- https://patchwork.kernel.org/patch/4843441/ - The patch provided here is already applied.

What could be the causes for read write error?

Also find attached schematic for reference.

[igorpadykov]

Hi Ritesh

errors may be related to signal integrity issues so one can try to tweak

drive strength settings (like IOMUXC_SW_PAD_CTL_PAD_SD*_DATA*) as on link

eMMC 8GB to 4GB - crash on linux (yocto) boot 

Best regards
igor
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[riteshpatel]

Hi Igor,

Thanks for your response.

We already set max drive strength for our board (Set DSE:111 40_Ohm). This is not working.

The same drive strength is set on iMX8M EVK.

Do we need to change slew rate too? We are setting up HS400 operating mode for eMMC.

Thanks.

[igorpadykov]

Hi Ritesh

yes one can change slew rate too. Drive strength may be different than on iMX8M EVK

since this is different board. Also one can heat/cool board.

If cooling down the part causes more failures, then it is likely the drive strength is
too high causing more overshoots and undershoots. If heating up the part causes more failures,
then the drive strength is too low and the signals may not rise/fall fast enough.

Best regards
igor

[riteshpatel]

Igor,

Thanks for the response. 

So what drive strength we should set for eMMC to run the device in cool & hot ambient environment?

Thanks, 

Ritesh

[igorpadykov]

Hi Ritesh

>what drive strength we should set for eMMC to run the device in cool & hot ambient environment?

you should find such settings yourself, experimentally and observing signals with oscilloscope.

Settings may be different on various boards and depend on board layout.

Best regards
igor