Can booting from emmc 5.1 with imx6q?

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Can booting from emmc 5.1 with imx6q?

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meizizhang
Contributor I

Hello! My custom board have a emmc device.It is KLMAG1JENB-B041,whose version is emmc 5.1.I can't boot from emmc directly!But I can boot from sd and then use the command "boot emmc" then jump to emmc, and run normal!

Can't The imx6q Processor support booting from emmc 5.1?I have a reference from EMMC 5.0 and EMMC 5.1 work on i.MX6 .But I can't confirm that,because somebody say it support booting from emmc 5.1 and another say it can't support.

barebox@Phytec phyCORE-i.MX6 Quad with eMMC:/ boot emmc
booting 'emmc'

Loading ARM Linux zImage '/mnt/emmc/zImage'
Loading devicetree from '/mnt/emmc/oftree'
Failed to fixup node in of_fixup_status+0x1/0x28: No such device
Failed to fixup node in of_fixup_status+0x1/0x28: No such device
Failed to fixup node in of_fixup_status+0x1/0x28: No such device
commandline: consoleblank=0 cma=265M@1G console=ttymxc0,115200n8 root=/dev/mmcblk3p2 rootflags=data=journal imxdrm.legacyfb_depth=32 rootwait ro fsck.repair=yes
exitcall-> nv_exit+0x1/0x20
exitcall-> devices_shutdown+0x1/0x28
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.1.46-i.MX6-PD16.1.1+ (meizi@Ubuntu-virtual-machine) (gcc version 5.3.0 (GCC) ) #3 SMP Sun Jun 30 15:25:09 CST 2019
[ 0.000000] CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] Machine model: Phytec phyBOARD-MIRA Quad Carrier-Board with eMMC
[ 0.000000] cma: Reserved 268 MiB at 0x40000000
[ 0.000000] Memory policy: Data cache writealloc
[ 0.000000] PERCPU: Embedded 11 pages/cpu @ee71d000 s15756 r8192 d21108 u45056
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 520720
[ 0.000000] Kernel command line: consoleblank=0 cma=265M@1G console=ttymxc0,115200n8 root=/dev/mmcblk3p2 rootflags=data=journal imxdrm.legacyfb_depth=32 rootwait ro fsck.repair=yes
[ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.000000] Dentry cache hash table entries: 262144 (order: 8, 1048576 bytes)
[ 0.000000] Inode-cache hash table entries: 131072 (order: 7, 524288 bytes)
[ 0.000000] Memory: 1792564K/2097152K available (7435K kernel code, 342K rwdata, 2644K rodata, 404K init, 415K bss, 30156K reserved, 274432K cma-reserved, 270336K highmem)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
[ 0.000000] vmalloc : 0xf0000000 - 0xff000000 ( 240 MB)
[ 0.000000] lowmem : 0x80000000 - 0xef800000 (1784 MB)
[ 0.000000] pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)
[ 0.000000] modules : 0x7f000000 - 0x7fe00000 ( 14 MB)
[ 0.000000] .text : 0x80008000 - 0x809e0084 (10081 kB)
[ 0.000000] .init : 0x809e1000 - 0x80a46000 ( 404 kB)
[ 0.000000] .data : 0x80a46000 - 0x80a9bba0 ( 343 kB)
[ 0.000000] .bss : 0x80a9bba0 - 0x80b03aac ( 416 kB)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[ 0.000000] Hierarchical RCU implementation.
[ 0.000000] Additional per-CPU info printed with stalls.
[ 0.000000] NR_IRQS:16 nr_irqs:16 16
[ 0.000000] L2C-310 erratum 769419 enabled
[ 0.000000] L2C-310 enabling early BRESP for Cortex-A9
[ 0.000000] L2C-310 full line of zeros enabled for Cortex-A9
[ 0.000000] L2C-310 ID prefetch enabled, offset 16 lines
[ 0.000000] L2C-310 dynamic clock gating enabled, standby mode enabled
[ 0.000000] L2C-310 cache controller enabled, 16 ways, 1024 kB
[ 0.000000] L2C-310: CACHE_ID 0x410000c7, AUX_CTRL 0x76470001
[ 0.000000] Switching to timer-based delay loop, resolution 333ns
[ 0.000016] sched_clock: 32 bits at 3000kHz, resolution 333ns, wraps every 715827882841ns
[ 0.000052] clocksource mxc_timer1: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 637086815595 ns
[ 0.001854] Console: colour dummy device 80x30
[ 0.001894] Calibrating delay loop (skipped), value calculated using timer frequency.. 6.00 BogoMIPS (lpj=30000)
[ 0.001920] pid_max: default: 32768 minimum: 301
[ 0.002125] Mount-cache hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.002150] Mountpoint-cache hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.003343] CPU: Testing write buffer coherency: ok
[ 0.003942] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.004116] Setting up static identity map for 0x10008280 - 0x100082f0
[ 0.007296] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[ 0.008373] CPU2: thread -1, cpu 2, socket 0, mpidr 80000002
[ 0.009427] CPU3: thread -1, cpu 3, socket 0, mpidr 80000003
[ 0.009578] Brought up 4 CPUs
[ 0.009622] SMP: Total of 4 processors activated (24.00 BogoMIPS).
[ 0.009637] CPU: All CPU(s) started in SVC mode.
[ 0.010551] devtmpfs: initialized
[ 0.032961] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4

……

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734 Views
igorpadykov
NXP Employee
NXP Employee

Hi meizi

issue may be related to signal integrity issues as described on

eMMC 8GB to 4GB - crash on linux (yocto) boot 

Best regards
igor
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