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KL28 LPSPI last bit not complete in continues PCS mode

Question asked by Liangliang Ma on Apr 18, 2017
Latest reply on Aug 22, 2019 by TomE

The last bit of a frame does not complete when CONT and CONTC bits are set in LPSPI TCR register, the SCK signal keeps high as the wave form in the attached picture. Is there any problem with register configuration, or it is designed like this?


I know that clear CONT and CONTC bits will complete the transfer and deassert PCS, but for the write-then-read operations which is the common use case of SPI bus, the CS signal must be kept asserted, and in that case the first frame received in the read operation has to be abandoned, as it is actually the last frame of the previous write operation. This is quite a dirty solution for the LPSPI driver and makes the SPI a asynchronous interface.