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MCF5270 I2C Master receive multiple bytes timing

Question asked by Carl Kugler on Mar 22, 2019
Latest reply on Apr 16, 2019 by Carl Kugler



I've asked this NetBurner Community Forum, but haven't seen any responses.


In I2C Master RX mode, after End of ADDR Cycle, after Dummy Read from I2DR, responding to IIF, not Last Byte to be Read, after slave has released clock stretch (SCL tristated), what is it that starts the clock going again so that the slave can transmit another byte? Is it the slave releasing SCL? Read from I2DR? The clearing of IIF? 


The reason I'm asking is that I'm wondering about the lifetime of valid data in I2DR. When does it start getting overwritten with new bits?


The block diagram* in MCF5271 Reference Manual shows an In/Out Data Shift Register. Should the received data get staged there until a Read from I2DR empties I2DR? What conditions might lead to an overflow?




* Figure 25-1. I2C Module Block Diagram, Document Number: MCF5271RM Rev. 2 07/2006