CW 8.8: Could not set PC to entry point.

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CW 8.8: Could not set PC to entry point.

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maheshwarreddy
Contributor I

I am using MPC 860 processor.  I could not able to debug the code with Code warrior USB TAP.  Getting an error "Could not set PC to entry point". But unable to correct this. Anybody is there to help?

Thank you

Best regards

Mahesh

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Pavel
NXP Employee
NXP Employee

Incorrect XFC connection produces incorrect SPLL behavior. It produce incorrect BDM or JTAG behavior. See the Section 14.2.2.3 of the MPC860 User's Manual:

https://www.nxp.com/docs/en/reference-manual/MPC860UM.pdf

Have a great day,
Pavel Chubakov

 

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Pavel
NXP Employee
NXP Employee

Check TRST connection on your board.

The TAP signals must be configured as follows to reset the scan chain logic: If both the TAP and low power mode are never used, connect TRST to ground. If the TAP or low power mode is used, connect TRST to PORESET. If power down mode (the lowest power mode, where VDDH is disabled) is used, connect TRST to PORESET through a diode (anode to TRST, cathode to PORESET). The TRST has internal pull-up resistor. Typical value of this resistor is about 5kOm but can vary by approximately a factor of 2.

 

Is there problem for connection if the MPC860FADS board is used?

Is there possibility to test your board and USB TAP under Windows XP?


Have a great day,
Pavel Chubakov

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Pavel
NXP Employee
NXP Employee

CodeWarrior 8.8 uses the MPC860 BDM interface for connection to the MPC8xx.

Do you use CodeWarrior 8.8 and the MPC860 BDM for debugging?

Have a great day,
Pavel Chubakov

 

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maheshwarreddy
Contributor I

We are using USB TAP with BDM connections but we are unable to enter into debug mode and flashing of code too.

Regards 

Maheshwar 

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Pavel
NXP Employee
NXP Employee

The DBGC field of the MPC860 Hard Reset Configuration is used for pin assigning of the IP_B[0–1]/IWP[0–1]/VFLS[0–1] pins. See the Table 11-3 of the MPC860 User's Manual.

 

The VFLS[0-1] signals of the BDM connector on the MPC8XXFADS board usually are connected to FRZ pin of MPC.

 

VFLS and FRZ signals are used to indicate debug mode of the processor. When both VFLS(0:1) are at '1', the MPC is in debug mode.

If FRZ is set, the MPC is in debug mode.

 

Check the SIUMCR[DBPC] value .

 

Have a great day,
Pavel Chubakov

 

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maheshwarreddy
Contributor I

When we are trying to enter into debug mode that time we are getting the JTAG clcok ,TDI,TDO and reset also then we are getting the error as failed to reset the target .The error is attached below .

Screenshot (30).png

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maheshwarreddy
Contributor I

Thank you for the reply.

The data pins of the external bus are connected PULL UP  of 3.3volts supply with the 4.7k resistor. But in the development board they are connected to the CPLD  is this makes any difference .Now also we are getting the same error as explained in the above .Whether VFLS[0,1] are in the control of the processor or with the external  events(user controlled ).

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Pavel
NXP Employee
NXP Employee

Incorrect XFC connection produces incorrect SPLL behavior. It produce incorrect BDM or JTAG behavior. See the Section 14.2.2.3 of the MPC860 User's Manual:

https://www.nxp.com/docs/en/reference-manual/MPC860UM.pdf

Have a great day,
Pavel Chubakov

 

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maheshwarreddy
Contributor I

Thank you for the reply. How to make this processor to work.Now we are trying to pull down the VDDSYN pin  to disable the SPLL . Now the processor is running with low frequency (according  to the user manual section 14.2.2.4 ) working with JTAG mode  or not . One more observation we made that is VFLS0 AND VFSL1 are in the low but according to the user manual these two pins must be high  right . But in our design we getting above mentioned pins in low state what may be the problem . Can you please suggest us in this regard.

Best regards 

Mahesh

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Pavel
NXP Employee
NXP Employee

Test your CodeWarrior TAP using static IP. See CodeWarrior TAP User Guide:

https://www.nxp.com/docs/en/user-guide/CWTAPUG.pdf

See simple example below.

 

  1. Set new static IP

core> netparam static_ip_address 192.168.3.111

core> netparam bootconfig static:lab01  // lab01 - it is name. you can set different name

core> reset

Have a great day,
Pavel Chubakov

 

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maheshwarreddy
Contributor I

Thank you for the reply. In the hardware design we are not connected the XFC pin to any where left open . But in the reference design this pin is connected to a capacitor with the VDDSYN supply.In the data sheet they mentioned  that the External filter capacitor for the PLL circuitry. Whether this will make any error towards JTAG debug.

Best regards

Mahesh

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Pavel
NXP Employee
NXP Employee

Test CCS connection to your board using the following commands in CCS console:

 (bin) 49 % config cc cwtap

(bin) 50 % show cc

 

The following commands also can be used:

(bin) 49 % log v

(bin) 50 % source IDcode.tcl

 

Is there connection to the CodeWarrior TAP and MPC860 if these commands are used?

Have a great day,
Pavel Chubakov

 

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maheshwarreddy
Contributor I

i have checked at  ccs.exe by using the above commands ,

after selecting the device and entering ip address of the pc, it is showing connection network timeout. please check the image and help us.

Screenshot (27).png

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Pavel
NXP Employee
NXP Employee

Usually similar error message happens if "Software Patch: CW PA v8.8.6 Windows " is not installed". See the following page:

https://nxp.flexnetoperations.com/control/frse/download?agree=Accept&element=6121541

 

This patch installs driver for CodeWarrior TAP.

Have a great day,
Pavel Chubakov

 

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maheshwarreddy
Contributor I

we already installed the patch and problem remains same ,

and sometimes it is showing error like

syntax error at line1

regards 

maheshwar

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