I have an FPGA endpoint connected to the MX6 as Gen1 x1. The logic in the FPGA is the DMA master doing DMA reads and writes through the MX6 root complex to host memory. Independently, each DMA channel is able to get respectable bandwidth of at least 1.5G bits per second on average. When I interleave reads and writes, however, the read bandwidth is severely reduced to about 700M bits per second.
I have learned that the MX6's PCIe device control register (PCIE_RC_DConR) settings can affect the flow control update rate. For example, the changing the Max_Payload_Size from 128 to 256 resulted in an improvement in the sustained bandwidth of the DMA write operations by increasing the FC credit update rate. Could a similar setting somewhere improve the simultaneous read / write capability?