iMX7 M4 LMEM DDR Caching

[dogisfat]

I have found a few different threads discussing the M4 cache controller:

JTAG debugger not working with enabled LMEM cache on M4 Core(iMX7) 

i.MX7D: atomic compare and swap instructions don't work with cache 

IMX7 M4 caching and execution speed 

The documentation on the controller is pretty sparse and a few of the threads indicate issues with the implementation of the cache controller. None of the reference material documents or scopes the issues which makes development particularly challenging. Would it be possible to get an improved list and scope of the issues in the LMEM cache controller?

I have experienced issues with the cache controller in the following areas:

• The reference manual documents that 0x8000_0000 - 0x8020_0000 is cacheable
  • Experimentally I have found 0x8000_0000 - 0x8040_0000 cacheable BUT 0x8020_0000 - 0x8040_0000 has some sort of bug that causes memory/instruction corruption.
  • I have also experimentally found that 0x8000_0000 - 0x8080_0000 is affected by the LMEM controller in some way. Setting a memory region at 0x8040_0000 to have the instruction access disabled results in a IACCVIOL despite no executable code living at or above that address, only the heap was linked to the address. Perhaps the cache controller is reading it as though it were executable?
• The Code Cache bus is doesn't provide any performance gain for "cacheable" DDR in the aliased 0x1000_0000 - 0x1FFE_FFFF memory range. There is no reference or documentation that the Code Cache bus is non-functional.

The biggest question I have at this point is:

Is there a workaround to the LMEM cache controller affecting the memory ranges 0x8020_0000 - 0x8080_0000? Or can a description of the issue be provided so I can understand what is and isn't safe from a code/data perspective.

[jimmychan]

this may help you https://community.nxp.com/message/1060291 

[dogisfat]

Jimmy,

The linked post doesn't really have any details about the specific questions I asked, the link discusses atomic operations and debuggers not working. I am looking for information on the LMEM controller that is accurate and descriptive of the actual implementation of the hardware since it is clear what is documented in the reference manual isn't represented in the hardware.

Thanks

[Yuri]

Hello,

  It is highly recommended to use 0x00000000 - 0x1FFFFFFF address range of

Cortex M address space for code, assuming it is optimized for instruction prefetch

and branch prediction. External memory (DRAM), located starting at 0x80000000,

is not intended for code; by default this region has Write Through cache policy,

which does not provide performance improvement for write operations.

 The DDR Code alias, mentioned in section 2.1.3 (Cortex-M4 Memory Map) of the

i.MX7 Reference Manual, Rev. 1, 01/2018, is not cacheable - according to

section 4.2.9.3.5 (Cache Function), where 0x1000_0000 - 0x1FFE_FFFF area

is not mentioned.

  CM4 address area 0x8000_0000 - 0x8020_0000 can be cacheable (for data).

Other regions should not be used for caching. As You wrote “ 0x8020_0000 - 0x8040_0000

has some sort of bug that causes memory/instruction corruption”.

From section 4.2.9.3.5 (Cache Function):

"    NOTE
To use cache, user needs to configure MPU to set those
memories as cacheable and all the other memories set as noncacheable."

Regards,

Yuri.