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Enabling UART8 port in imx6ul

Question asked by chandra sekhar on Sep 11, 2018
Latest reply on Sep 14, 2018 by chandra sekhar


I have gone through the How-To use UART7/8 on i.MX6UL this document,

as per the document if you dont enable ENET driver uart8 driver should work without making any extra changes.

I am not enabling ethernet in my device tree and enabling UART8 still kernel hangs while booting.  below is my dts file for uart8

 pinctrl_uart8: uart8grp {
            fsl,pins = <
                MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX  0x1b0b1
                MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX     0x1b0b1

I dont have any CTS/RTS pins 
Below is the kernel log


U-Boot 2015.04 (May 03 2018 - 17:44:11)


CPU: Freescale i.MX6UL rev1.2 at 396 MHz
CPU: Temperature 45 C
Reset cause: POR
Board: ESYS-PLUM-V0.01
Platen sense is 1
Paper sense is 0
I2C: ready
DRAM: 128 MiB
NAND: 128 MiB
*** Warning - bad CRC, using default environment


In: serial
Out: serial
Err: serial
Net: CPU Net Initialization Failed
No ethernet found.
Normal Boot
Hit any key to stop autoboot: 0


NAND read: device 0 offset 0x200000, size 0x700000
7340032 bytes read: OK


NAND read: device 0 offset 0x900000, size 0x100000
1048576 bytes read: OK
Kernel image @ 0x80800000 [ 0x000000 - 0x303be8 ]
## Flattened Device Tree blob at 83000000
Booting using the fdt blob at 0x83000000
Using Device Tree in place at 83000000, end 83009d7a


Starting kernel ...


Booting Linux on physical CPU 0x0
Linux version 3.14.38-6UL_ga-mfgtool+ge4944a5 (chandra@osboxes) (gcc version 4.9.2 (GCC) ) #131 SMP PREEMPT Tue Sep 11 16:49:50 IST 2018
CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine model: Freescale i.MX6 UltraLite 14x14 EVK Board
Memory policy: Data cache writealloc
PERCPU: Embedded 7 pages/cpu @87ee4000 s7680 r8192 d12800 u32768
Built 1 zonelists in Zone order, mobility grouping off. Total pages: 32512
Kernel command line: console=ttymxc0,115200 ubi.mtd=4 root=ubi0:rootfs rw rootfstype=ubifs mtdparts=gpmi-nand:2m(boot),7m(kernel),1m(dtb),100m(rootfs),-(user)
PID hash table entries: 512 (order: -1, 2048 bytes)
Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
Memory: 123824K/131072K available (3815K kernel code, 219K rwdata, 1320K rodata, 299K init, 321K bss, 7248K reserved)
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
vmalloc : 0x88800000 - 0xff000000 (1896 MB)
lowmem : 0x80000000 - 0x88000000 ( 128 MB)
modules : 0x7f000000 - 0x80000000 ( 16 MB)
.text : 0x80008000 - 0x8050c020 (5137 kB)
.init : 0x8050d000 - 0x80557e00 ( 300 kB)
.data : 0x80558000 - 0x8058ece0 ( 220 kB)
.bss : 0x8058ecec - 0x805df0f8 ( 322 kB)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Preemptible hierarchical RCU implementation.
RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=1.
RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
NR_IRQS:16 nr_irqs:16 16
Switching to timer-based delay loop
sched_clock: 32 bits at 3000kHz, resolution 333ns, wraps every 1431655765682ns
clocksource_of_init: no matching clocksources found
Console: colour dummy device 80x30
Calibrating delay loop (skipped), value calculated using timer frequency.. 6.00 BogoMIPS (lpj=30000)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
CPU: Testing write buffer coherency: ok
/cpus/cpu@0 missing clock-frequency property
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x803a2d58 - 0x803a2db0
Brought up 1 CPUs
SMP: Total of 1 processors activated (6.00 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 2 part 30 variant 7 rev 5
pinctrl core: initialized pinctrl subsystem
regulator-dummy: no parameters
DMA: preallocated 256 KiB pool for atomic coherent allocations
cpuidle: using governor ladder
cpuidle: using governor menu
Use WDOG1 as reset source
syscon 20c8000.anatop: regmap [mem 0x020c8000-0x020c8fff] registered
vdd3p0: 2625 <--> 3400 mV at 3000 mV
cpu: 725 <--> 1450 mV at 1150 mV
vddsoc: 725 <--> 1450 mV at 1175 mV
syscon 20e4000.iomuxc-gpr: regmap [mem 0x020e4000-0x020e7fff] registered
syscon 21ac000.romcp: regmap [mem 0x021ac000-0x021affff] registered
syscon 21bc000.ocotp-ctrl: regmap [mem 0x021bc000-0x021bffff] registered
hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 8 bytes.
imx6ul-pinctrl 20e0000.iomuxc: initialized IMX pinctrl driver
20dc000.gpc supply pu not found, using dummy regulator
bio: create slab <bio-0> at 0
mxs-dma 1804000.dma-apbh: initialized
vref-3v3: 3300 mV
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
i2c i2c-2: IMX I2C adapter registered
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <>
PTP clock support registered
Switched to clocksource mxc_timer1
imx rpmsg driver is registered.
Bus freq driver module loaded
futex hash table entries: 256 (order: 2, 16384 bytes)
VFS: Disk quotas dquot_6.5.2
Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
msgmni has been set to 241
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
imx-weim 21b8000.weim: Driver registered.
imx-sdma 20ec000.sdma: no event needs to be remapped
imx-sdma 20ec000.sdma: loaded firmware 3.1
imx-sdma 20ec000.sdma: initialized
Serial: IMX driver
2020000.serial: ttymxc0 at MMIO 0x2020000 (irq = 58, base_baud = 5000000) is a IMX
console [ttymxc0] enabled