My custom hardware is based on i.MX6Q processor and 800MHz Alliance DDR3 memory AS4C256M16D3A-12BCN.Design is most related to Nitrogen6_max design.
I set tCL = 6 and tCWL = 8 for the calibration and ddr init script. Some boards are working for this values and for some boards I had to change tCWL = 7 for better performance. Otherwise getting segmentation faults.
1) How this could happen with the same ddr layout and same production line boards ? What can we figure with this fine tuning of tCL and tCWL value of board to board ?
A well as I could see following write DQS delays for my boards. You can see DQS 3 and DQS 4 are way off. It should be lover than 1/8 according to NXP user manual.
2) What can we say from following DQS results ? Is it a impedance problem of those byte lanes ?
3) To optimize above values I used following method. But I couldn't see any impact for DQS 3 and DQS 4 with WALAT changes. Why is that ?
4) What are the other dependency which we can tolerate like tCWL and tCL for the memory performance ?
Here I have attached DDR3 memory data sheet and NXP calibration tool results.
I must be thankful to you if you will kindly reply me soon.