RT1050 SDRAM clock configuration

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RT1050 SDRAM clock configuration

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joshuasakwa
Contributor II

I couldn't find a note on how to configure the clock for specific SDRAM part, but noticed that in in the SEMC example there are a couple of clues:

  • a define: EXAMPLE_SEMC_CLK_FREQ
  • a comment: /* Set semc clock to 132Mhz */

 

if EXAMPLE_SEMC_CLK_FREQ is printed the value is: 109241376 -- I was anticipating 132MHz (based on the comment and the functionality described in the application note: https://www.nxp.com/docs/en/application-note/AN12077.pdf

 

Based on experimentation with the value 'N' passed as the second argument to: CLOCK_SetDiv(kCLOCK_SemcDiv, N) -- where N ranges from 1..7, EXAMPLE_SEMC_CLK_FREQ ranges from: 163862064..40965516 

  • What is the actual clock speed configured by default in the SEMC example (132MHz or 109.2MHz)?
  • Does the 109.2MHz value indicate that the core clock is not 600MHz?
  • Does this correspond to the clocking of the SDRAM at 109.2MHz (or 132) -- not 167MHz as reported in the EVK user guide?
  • What are the acceptable range of values for kCLOCK_SemcDiv?
  • If the value of kCLOCK_SemcDiv is modified from the default, does that change the units of the sdramconfig data structure passed to SEMC_ConfigureSDRAM, or are these units scaled automatically?
  • the math: "sdramconfig.tCkeOff_Ns = (1000000000 / clockFrq);" rounds down, should I be concerned that the setting might be too aggressive? 

 

Many thanks in advance!

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3 Replies

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weidong_sun
NXP TechSupport
NXP TechSupport

Hello Joshua,

 See the link, please!

https://community.nxp.com/docs/DOC-340813 

After understanding how to configure registers related to SDRAM clock, go back to configure it in SDK.

Have a nice day!

TIC weidong sun

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joshuasakwa
Contributor II

Hello Wigros, 

I parsed out the register values, and followed the math in the Clock Config note that you forwarded. I arrive at the same 109.2 MHz clock value that was computed by the MCU API functions. To confirm my understanding, a few follow up questions:

1. does this mean that 109.2MHz is the clock being applied to the SDRAM?

2. is it safe to change these various clock dividers to arrive at a different frequency, and if so what is the acceptable range?

3. the math: "sdramconfig.tCkeOff_Ns = (1000000000 / clockFrq);" rounds down, should I be concerned that the setting might be too aggressive? 

Thanks again for your help!

Joshua

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joshuasakwa
Contributor II

Thanks TIC -- this is great information! I will study it.

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