MK22FN1M0AVLH12 FTM2 Two clock gates?

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MK22FN1M0AVLH12 FTM2 Two clock gates?

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mathol
Contributor I


Hi!

 

I am using the MK22FN1M0AVLH12 in a project, and need to use all of the FTMs. Everything was fine until i tried to initialize the FTM2 with the FTM_Init() found in the KSDK. It was hardfaulting, with IMPRECISERR code. After looking through i suspected that there was something wrong with the clock, as i could not read the registers with the debugger when the FTM2 clock gate (SIM->SCGC6). When testing the other FTMs with the debugger i stumbled upon another FTM2 clock gate value in SIM->SCGC3, next to the FTM3 clock gate. When enabling this value, the FTM2 responded. I also looked in the datasheet (K22P64M120SF5V2RM) and both of these gate registry entries are listed, with the same description.

 

The KSDK clock driver is using the SCGC6 registry entry when enabling the FTM2. As this does not activate the clock for the FTM2, the system hardfaults. Changing the driver to enable the FTM2 value in SCGC3, the system works without hardfaulting.

 

Is this a fault in the driver, in the chip design or in the datasheet? Or maybe all of them.

 

Best regards
Matias Holsve

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Victor_dV
Contributor I

Hi, using a MK21fx512AVMD12, 

with MCUXpresso IDE v11.4.1 [Build 6260] [2021-09-15]

sdk: 2.3.1

 

This bug is still present in march 2022. 

 

best regards.

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zhongshen
Contributor III

Hi,

So far there is still the same issue on the

 latest SDK with MCUXpresso!

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jorge_a_vazquez
NXP Employee
NXP Employee

Hi Matias Holsve

That device has two peripheral AIPS buses, with some peripherals on one bus, and others in the other bus. The FTM2 peripheral is available on both buses and, as you said, if you look at the addresses for the FTM2 register, it shows two sets of register, so, there are two clock gates for the FTM2 and you need to enable the clock gate associated with the set register that will be used. That's why there are two clock gates for the FTM2.

SDK clock driver for FTM has a bug and when you enable the gate for FTM2, it enable the associated FTM2 gate in SIM_SCGC3 register, when you actually need the associated FTM2 gate in the SIM_SCG6 register. The workaround for this issue is add the line SIM_SCGC6 |= SIM_SCGC6_FTM2_MASK;


We already award of this problem and we are working to resolve it.
Hope this information helps you and please tell us any question related.


Have a great day
Jorge Alcala

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