Q&A: Does iMX6Q/DL WEIM support unaligned access?

Document created by Yixing Kong Employee on Nov 11, 2013
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Question:

An alignement trap in Linux had been seen in an unaligned access of the WEIM (to an external FPGA)

 

Alignment trap: testFPGA (1027) PC=0x000086dc Instr=0xe1d330b0 Address=0x08000001 FSR 0x011

The issue can be reproduced with the platform SDK EIM parallel Nor Test on the Sabre AI - When I access WEIM_BASE_ADDR +1 I get an exception.

 

EIM test start:
Flash size: 0x 2000000
Flash erase...
.
Oops, data abort occurred!

Registers at point of exception:
cpsr = nZCvqeAift Supervisor (0x60000113)
r0 = 0x00000000    r8 =  0x00000000
r1 = 0x00000000    r9 =  0x00000000
r2 = 0x00000001    r10 = 0x00000000
r3 = 0x08000001    r11 = 0x10409770
r4 = 0xdeadfeed    r12 = 0x00000001
r5 = 0x10002458    sp =  0x10409734
r6 = 0x00000000    lr =  0x1000ef9c
r7 = 0x00000094    pc =  0x1000bfd0
dfsr = 0x00000001
dfar = 0x08000001

Access type: read
Fault status: 0x1

 

Is adress alligned access mandatory for EIM or AXI HW? or is it possible to support unaligned access?

 

Answer:

EIM should support unaligned access. Also ARM architecture supports unaligned access to data and address buses but only if the MMU co-processor is setup for that.

Try checking cp15 sctlr[1]. Linux discourage the access to unaligned memory and some times that makes a bus error resulting in a kernel panic. So the drivers and the setup architecture files should support unaligned memory access.

ARM Information Center

/linux/Documentation/unaligned-memory-access.txt

 

The EIM device is a AXI slave which should support unaligned access. Reference Manual and there's a sub-chapter in the EIM call AXI(Master) Bus cycles support. In that chapter there's a table AXI to Memory Burst Splits Number in that table states the increment burst access to a aligned or unaligned address. I expect those are for the EIM and not refer only to the AXI bus.

At any case is not state clear if unaligned access should work only in burst mode (which doesn't make any sense to me) or if the RM information is incorrect. Also in the same chapter in signals not supported never list the alignment signals so unaligned access is supported.

 

Link with some generic ARM information about that.

http://forums.arm.com/index.php?/topic/8862-axi-narrowunaligned-read-transfers/

AXI4 - Aligned & unaligned address - ARM Community

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