The following contradicting information regarding the UART clock tree has been seen in the Rev. 1.0 version of the reference manual:
PLL3_PFD1 -> divide by 6 -> adjustable post divider -> UART
PLL3 -> divide by 6 -> UART
In the old Rev D I found:
PLL3 -> divide by 6 ... and something about 80MHz
The assumption is that correct path would be:
PLL3 -> divide by 6 -> post divider -> UART.
The designer said that UART _CLK_ROOT comes from PLL3 (not PLL3:PFD1) and is divided by 6 to produce 80 MHz.
I'm waiting for him to confirm that the divider he mentions is CSCDR1[UART_CLK_PODF].