Q&A: Errors in the i.MX6 reference manual regarding the clock tree for the UART

Document created by Yixing Kong Employee on Sep 23, 2013
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The following contradicting information regarding the UART clock tree has been seen in the Rev. 1.0  version of the reference manual:

Page 813:

PLL3_PFD1 -> divide by 6 -> adjustable post divider -> UART


Page 839:

PLL3 -> divide by 6 -> UART


In the old Rev D I found:

Page 803:

PLL3 -> divide by 6  ... and something about 80MHz

The assumption is that correct path would be:

PLL3 -> divide by 6 -> post divider -> UART.



The designer said that UART _CLK_ROOT comes from PLL3 (not PLL3:PFD1) and is divided by 6 to produce 80 MHz.

I'm waiting for him to confirm that the divider he mentions is CSCDR1[UART_CLK_PODF].

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