1. Are there any hardware limitations (such as in the Host Controller IP block itself, how this IP block was implemented or in the DMA engine) to how many device endpoints the i.MX53 can handle on Host2 or Host3? The Reference Manual notes that the OTG controller supports up to 8 endpoints but does not provide information on the Host Controller.
2. Do any of the device validation tests for verifying the i.MX53 design (or USB cert tests) test compatibility/performance with multiple devices and multiple endpoints?
3. What are the maximum number of endpoints Freescale has tested with?
During extensive testing the customer observes 100% CPU utilization with only 6 endpoints (can be a combination of multi-endpoint devices or single-endpoint devices - see below for test configuration details) using our latest Linux reference BSP (2.6.35 Kernel). They have tested with the Adeneo WEC7 BSP and the open source Linux kernel based on 3.11 for the QSB and have observed similar performance limitations. This has been tested with multiple packet sizes and device/endpoint configurations and no impact has been shown in varying these parameters.
The customer did note that they are only receiving/processing a single interrupt at the 1ms boundary regardless of the number of devices/endpoints. Processing this interrupt takes approximately 23us for one device and an additional 17us for each additional device endpoint after the first that is processed.
The customer hardware configuration for their testing looks something like this:
On the customer's board:
[i.MX53 Host2/Host3] -> [SMSC 3315 USB High Speed ULPI PHY] -> [SMSC LAN9514 On-board 4-port USB 2.0 HS Hub]
[SMSC LAN9514 Port #1] -> [SMSC USB2415 4-Port USB 2.0 HS Hub] -> Medical device w/ endpoints #1-4
[SMSC LAN9514 Port #2] -> [SMSC USB2415 4-Port USB 2.0 HS Hub] -> Medical device w/ endpoints #5-8
[SMSC LAN9514 Port #3] -> Medical device w/ endpoint #9
[SMSC LAN9514 Port #4] -> Medical device w/ endpoint #10
Hosts do not have endpoints. Only devices have endpoints.
EHCI compliance hosts, like all i.MX devices, use a linked list of queues (for bulk/control transport). Each queue has a queuehead that represents a corresponding endpoint and has the endpoint's capabilities. On the queue are transfer descriptors that have the information of which data is to be moved to/from the endpoint of the device. All of this is in main memory and read/written under DMA. There is no limit on how many devices/endpoints a host can service, other than the amount of available main memory (DRAM).
The CPU has to build the linked lists, but this is normally not taking much bandwidth.
My guess at this time is that there may be a problem in the USB driver, or the application that is using the driver, or a problem with data alignment. For efficient operation, data must be aligned on 32-bit boundaries. Buffers are best aligned on 64-byte boundaries.