Q&A: What is the Min LPDDR2 clock frequency allowed by the i.MX6?

Document created by Yixing Kong Employee on Aug 22, 2013
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Q:

What is the Min LPDDR2 clock frequency allowed by the i.MX6?
The Jedec Spec for LPDDR2 allows for a min tck period of 100ns. Are there any required relashionship between the DDR clock frequency and other clocks in the i.MX6?

 

A:
The JEDEC maximum period for the MX6 is 100nS as per the LPDDR2 specification.  There is a minimum period during boot, before everything is configured and fully up to speed of 18nS.

 

Are you saying the imx6 memory controller can operatate down to the min frequecies specified in the LPDDR2 JEDEC spec?

 

Given that there is no limit specified in the data sheet, it should operate that slowly, provided the clocking can be set for it to operate so slowly.

 

I would imagine that the core will need to be running slowly as well, since it does not make sense to slow the memory bus without slowing the core down as well.

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