These questions and answers are about interrupt generation at a dedicated (configurable) video output port.
The i.MX6D manual (Rev. 0) Image Processing Unit (IPU) chapter mentions:
- Every DI has 10 timing generator counters.
- The IPU Interrupt Generator has 10 DI0 counters (1...10) and just 2 DI1 counters (3 & 8) as interrupt sources.
- The Interrupt Control Register lists 11 DI0 counters (0...10)
Q1. Are the DI timing-generator counters linked to the counters in the interrupt controller, or are they different counters?
A1. Yes, the DI timing generator counters are linked to the counters in the interrupt controller.
Q2. Why are there 11 counters listed in the interrupt controller, but just 10 counters in the timing generator?
A2. There is disp_clk_en_pre in the interrupt controller. Thus the 11 counters: 10 timing generator counters and 1 disp clock generator counter.
Q3. Is configurable timing feasible for DI0 by using the timing generator counters?
A3. Yes, using the 10 internal timing counters you can generate various timing relationships. In addition, you can detect any of the interrupt counters. For example, if you use counter 8, then you can detect the interrupt associated with counter 8.
Q4. Explain the impact of the DI1 counter access of only channels 3 and 8.
A4. DI1 also has 10 timing generator counters and 1 disp clock generator counter, which you can use to generate desired waveforms. This is similar to DI0.
The difference is only 2 of the 10 counters (plus another disp_clk) are connected to the interrupt controller for DI1. Therefore, there is a restriction for detection. If you use counter 7, read out the counter 7 interrupt of DI1 is not possible.
However, 2 channels should be sufficient. These interrupts are usually used to indicate a frame start or a frame end. We usually use counter 3 to represent Vsync. So normally we only use counter 3 interrupt. DI1 has only 3 accesses because this covers the anticipated use case and the desire was to restrict register size. The extra counters facilitate flexible DI1 timing generation.