i.MX25: When Using 120MHz UPLL as Clock Source, GPT Counter Returns Unexpected Results

Document created by Qiang Li Employee on Dec 17, 2012Last modified by Jodi Paul on May 20, 2013
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Some i.MX25 customers reported an issue for the GPT timer, when using 120MHz (240MHz UPLL divided 2) clock source as the GPT per_clk, the timer will not be increased all the time in free-run mode. If using 66.5MHz IPG clock and 133MHz PER clock as the clock source, there are no such issue.

 

There are 4 test cases in the attached test code.

Case 0: in CCM_MCR, set bit 5 as 0 for 133MHz HCLK as the gpt_per_clk source;  in GPT_CR bit[8:6], set 0b001 ipg_clk (66.5MHz). There is no issue, the GPT counter is fixed at 4 between old_cnt and new_cnt.

Case 1: in CCM_MCR, set bit 5 as 0 for 133MHz HCLK as the gpt_per_clk source;  in GPT_CR bit[8:6], set 0b010 ipg_clk_highfreq (133MHz). There is no issue, the GPT counter is fixed at 8 between old_cnt and new_cnt.

Case 2: in CCM_MCR, set bit 5 as 1 for 240MHz UPLL divided by 2 as the gpt_per_clk source;  in GPT_CR bit[8:6], set 0b001 ipg_clk (60MHz). There is no issue, the GPT counter is fixed at 4 between old_cnt and new_cnt.

Case 3: in CCM_MCR, set bit 5 as 0 for 240MHz UPLL divided by 2 as the gpt_per_clk source;  in GPT_CR bit[8:6], set 0b010 ipg_clk_highfreq (120MHz). There is issue, the GPT counter is not a fixed value between old_cnt and new_cnt, and sometimes it will be negative.

 

 

Count 9874: 4

old_cnt: 0x188849dc

new_cnt: 0x188849e0

Count 9877: 12

old_cnt: 0x18918400

new_cnt: 0x1891840c

Count 9915: 4

old_cnt: 0x189aea90

new_cnt: 0x189aea94

Count 9937: -12

old_cnt: 0x18a42458

new_cnt: 0x18a4244c

Count 9967: 4

old_cnt: 0x18adb17c

new_cnt: 0x18adb180

 

In fact, it is not an issue, when using UPLL as the GPT clock source, the maxim frequency should be 60MHz. That's why all other three test case is OK and it only failed on this case.

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