Prevent PMIC PF0100 Backfeed on i.MX6 Designs

Document created by DavidBabin Employee on Nov 20, 2012Last modified by DavidBabin Employee on Apr 10, 2013
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Freescale's PF0100 PMIC should have VDDIO power tied to the same supply as the associated I2C supply on MX6.


There is a momentary on-chip sneak path on power-up if VDDIO is wired per the i.MX6 SABRE-AI automotive development platform. As a result, I2C power rail P3V3_DELAYED rises prematurely due to backfeed from P3V3 through the I2C port.

Note that on SABRE-AI, P3V3 powers up before P3V3_DELAYED.


Existing SABRE-AI design: PF0100 VDDIO is wired to P3V3.

Corrective action for mass production: Wire PF0100 VDDIO to P3V3_DELAYED; same supply as the associated I2C supplies on MX6 (NVCC_EIM0 and NVCC_GPIO).


Laboratory results attached.